[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 5/8] target-xtensa: implement MISC SR
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 5/8] target-xtensa: implement MISC SR |
Date: |
Wed, 5 Dec 2012 07:15:24 +0400 |
The Miscellaneous Special Registers Option provides zero to four scratch
registers within the processor readable and writable by RSR, WSR, and
XSR. These registers are privileged. They may be useful for some
application-specific exception and interrupt processing tasks in the
kernel. The MISC registers are undefined after reset.
See ISA, 4.7.3 for details.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/cpu.h | 1 +
target-xtensa/overlay_tool.h | 1 +
target-xtensa/translate.c | 4 ++++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index a73d32d..08fd5bc 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -153,6 +153,7 @@ enum {
ICOUNTLEVEL = 237,
EXCVADDR = 238,
CCOMPARE = 240,
+ MISC = 244,
};
#define PS_INTLEVEL 0xf
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
index 0b47029..dd4f51a 100644
--- a/target-xtensa/overlay_tool.h
+++ b/target-xtensa/overlay_tool.h
@@ -95,6 +95,7 @@
/* Other, TODO */ \
XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
+ XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index fbeac7f..48a22de 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -179,6 +179,10 @@ static const XtensaReg sregnames[256] = {
XTENSA_OPTION_TIMER_INTERRUPT),
[CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
XTENSA_OPTION_TIMER_INTERRUPT),
+ [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
+ [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
+ [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
+ [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
};
static const XtensaReg uregnames[256] = {
--
1.7.7.6
- [Qemu-devel] [PATCH 0/8] xtensa patch queue, Max Filippov, 2012/12/04
- [Qemu-devel] [PATCH 2/8] target-xtensa: implement CACHEATTR SR, Max Filippov, 2012/12/04
- [Qemu-devel] [PATCH 1/8] target-xtensa: implement ATOMCTL SR, Max Filippov, 2012/12/04
- [Qemu-devel] [PATCH 4/8] target-xtensa: better control rsr/wsr/xsr access to SRs, Max Filippov, 2012/12/04
- [Qemu-devel] [PATCH 3/8] target-xtensa: restrict available SRs by enabled options, Max Filippov, 2012/12/04
- [Qemu-devel] [PATCH 5/8] target-xtensa: implement MISC SR,
Max Filippov <=
- [Qemu-devel] [PATCH 6/8] target-xtensa: add SR accessibility unit tests, Max Filippov, 2012/12/04
- [Qemu-devel] [PATCH 7/8] target-xtensa: add s32c1i unit tests, Max Filippov, 2012/12/04
- [Qemu-devel] [PATCH 8/8] target-xtensa: use movcond where possible, Max Filippov, 2012/12/04
- Re: [Qemu-devel] [PATCH 0/8] xtensa patch queue, Blue Swirl, 2012/12/08