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[Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14


From: Alexander Graf
Subject: [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14
Date: Fri, 14 Dec 2012 13:13:16 +0100

Hi Blue / Aurelien,

This is my current patch queue for ppc.  Please pull.

Alex


The following changes since commit 1c97e303d4ea80a2691334b0febe87a50660f99d:
  Anthony Liguori (1):
        Merge remote-tracking branch 'afaerber/qom-cpu' into staging

are available in the git repository at:

  git://repo.or.cz/qemu/agraf.git ppc-for-upstream

Alexander Graf (27):
      openpic: Remove unused code
      mpic: Unify numbering scheme
      openpic: update to proper memory api
      openpic: combine mpic and openpic src handlers
      openpic: Convert subregions to memory api
      openpic: combine mpic and openpic irq raise functions
      openpic: merge mpic and openpic timer handling
      openpic: combine openpic and mpic reset functions
      openpic: unify memory api subregions
      openpic: remove unused type variable
      openpic: convert simple reg operations to builtin bitops
      openpic: rename openpic_t to OpenPICState
      openpic: remove irq_out
      openpic: convert to qdev
      openpic: make brr1 model specific
      openpic: add Shared MSI support
      PPC: e500: Add MSI support
      PPC: e500: Declare pci bridge as bridge
      MSI-X: Fix endianness
      openpic: fix minor coding style issues
      openpic: Accelerate pending irq search
      PPC: E500: PCI: Make first slot qdev settable
      PPC: E500: PCI: Make IRQ calculation more generic
      PPC: E500: Generate dt pci irq map dynamically
      PPC: E500: Move PCI slot information into params
      PPC: E500plat: Make a lot of PCI slots available
      PPC: e500: pci: Export slot2irq calculation

Ben Herrenschmidt (2):
      pseries: Use #define for XICS base irq number
      pseries: Allow RTAS tokens without a qemu handler

Bharat Bhushan (2):
      e500: Adding CCSR memory region
      Adding BAR0 for e500 PCI controller

David Gibson (8):
      pseries: Fix incorrect initialization of interrupt controller
      pseries: Add tracepoints to the XICS interrupt controller
      pseries: Split xics irq configuration from state information
      pseries: Implement PAPR NVRAM
      pseries: Update SLOF for NVRAM support
      pseries: Don't allow TCE (iommu) tables to be registered with duplicate 
LIOBNs
      target-ppc: Don't use hwaddr to represent hardware state
      pseries: Increase default NVRAM size

Michael Ellerman (1):
      pseries: Return the token when we register an RTAS call

 hw/msix.c            |    6 +-
 hw/openpic.c         | 1397 ++++++++++++++++++--------------------------------
 hw/openpic.h         |    7 +-
 hw/ppc/Makefile.objs |    2 +-
 hw/ppc/e500-ccsr.h   |   17 +
 hw/ppc/e500.c        |  205 ++++++--
 hw/ppc/e500.h        |    2 +
 hw/ppc/e500plat.c    |    3 +
 hw/ppc/mpc8544ds.c   |    2 +
 hw/ppc_newworld.c    |   25 +-
 hw/ppce500_pci.c     |   58 ++-
 hw/ppce500_pci.h     |    9 +
 hw/spapr.c           |   35 ++-
 hw/spapr.h           |    4 +-
 hw/spapr_iommu.c     |    6 +
 hw/spapr_nvram.c     |  196 +++++++
 hw/spapr_rtas.c      |    6 +-
 hw/xics.c            |   47 ++-
 hw/xics.h            |    1 +
 pc-bios/README       |    2 +-
 pc-bios/slof.bin     |  Bin 878640 -> 880832 bytes
 qemu-config.c        |    4 +
 roms/SLOF            |    2 +-
 target-ppc/cpu.h     |    2 +-
 trace-events         |   13 +
 25 files changed, 1043 insertions(+), 1008 deletions(-)
 create mode 100644 hw/ppc/e500-ccsr.h
 create mode 100644 hw/ppce500_pci.h
 create mode 100644 hw/spapr_nvram.c



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