Re: [Qemu-devel] [PATCH 25/40] openpic: convert to qdev

[Blue Swirl]

On Fri, Dec 14, 2012 at 8:42 PM, Alexander Graf <address@hidden> wrote:
>
> On 14.12.2012, at 21:32, Blue Swirl wrote:
>
>> On Fri, Dec 14, 2012 at 12:13 PM, Alexander Graf <address@hidden> wrote:
>>> This patch converts the OpenPIC device to qdev. Along the way it
>>> renames the "openpic" target to "raven" and the "mpic" target to
>>> "fsl_mpic_20", to better reflect the actual models they implement.
>>>
>>> This way we have a generic OpenPIC device now that can handle
>>> different flavors of the OpenPIC specification.
>>>
>>> Signed-off-by: Alexander Graf <address@hidden>
>>> ---
>>> hw/openpic.c      |  278 
>>> ++++++++++++++++++++++++++---------------------------
>>> hw/openpic.h      |    8 +-
>>> hw/ppc/e500.c     |   24 ++++-
>>> hw/ppc_newworld.c |   25 +++++-
>>> 4 files changed, 180 insertions(+), 155 deletions(-)
>>>
>>> diff --git a/hw/openpic.c b/hw/openpic.c
>>> index 5116b3e..591b291 100644
>>> --- a/hw/openpic.c
>>> +++ b/hw/openpic.c
>>> @@ -37,6 +37,7 @@
>>> #include "ppc_mac.h"
>>> #include "pci.h"
>>> #include "openpic.h"
>>> +#include "sysbus.h"
>>>
>>> //#define DEBUG_OPENPIC
>>>
>>> @@ -54,30 +55,10 @@
>>> #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
>>> #define VID         0x03 /* MPIC version ID */
>>>
>>> -enum {
>>> -    IRQ_IPVP = 0,
>>> -    IRQ_IDE,
>>> -};
>>> -
>>> -/* OpenPIC */
>>> -#define OPENPIC_MAX_CPU      2
>>> -#define OPENPIC_MAX_IRQ     64
>>> -#define OPENPIC_EXT_IRQ     48
>>> -#define OPENPIC_MAX_TMR      MAX_TMR
>>> -#define OPENPIC_MAX_IPI      MAX_IPI
>>> -
>>> -/* Interrupt definitions */
>>> -#define OPENPIC_IRQ_FE     (OPENPIC_EXT_IRQ)     /* Internal functional 
>>> IRQ */
>>> -#define OPENPIC_IRQ_ERR    (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
>>> -#define OPENPIC_IRQ_TIM0   (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
>>> -#if OPENPIC_MAX_IPI > 0
>>> -#define OPENPIC_IRQ_IPI0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First 
>>> IPI IRQ */
>>> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * 
>>> OPENPIC_MAX_IPI)) /* First doorbell IRQ */
>>> -#else
>>> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First 
>>> doorbell IRQ */
>>> -#define OPENPIC_IRQ_MBX0   (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First 
>>> mailbox IRQ */
>>> -#endif
>>> +/* OpenPIC capability flags */
>>> +#define OPENPIC_FLAG_IDE_CRIT     (1 << 0)
>>>
>>> +/* OpenPIC address map */
>>> #define OPENPIC_GLB_REG_START        0x0
>>> #define OPENPIC_GLB_REG_SIZE         0x10F0
>>> #define OPENPIC_TMR_REG_START        0x10F0
>>> @@ -87,31 +68,37 @@ enum {
>>> #define OPENPIC_CPU_REG_START        0x20000
>>> #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>>>
>>> -/* MPIC */
>>> -#define MPIC_MAX_CPU      1
>>> -#define MPIC_MAX_EXT     12
>>> -#define MPIC_MAX_INT     64
>>> -#define MPIC_MAX_IRQ     MAX_IRQ
>>> +/* Raven */
>>> +#define RAVEN_MAX_CPU      2
>>> +#define RAVEN_MAX_EXT     48
>>> +#define RAVEN_MAX_IRQ     64
>>> +#define RAVEN_MAX_TMR      MAX_TMR
>>> +#define RAVEN_MAX_IPI      MAX_IPI
>>> +
>>> +/* Interrupt definitions */
>>> +#define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
>>> +#define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
>>> +#define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
>>> +#define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ 
>>> */
>>> +/* First doorbell IRQ */
>>> +#define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
>>> +
>>> +/* FSL_MPIC_20 */
>>> +#define FSL_MPIC_20_MAX_CPU      1
>>> +#define FSL_MPIC_20_MAX_EXT     12
>>> +#define FSL_MPIC_20_MAX_INT     64
>>> +#define FSL_MPIC_20_MAX_IRQ     MAX_IRQ
>>>
>>> /* Interrupt definitions */
>>> /* IRQs, accessible through the IRQ region */
>>> -#define MPIC_EXT_IRQ      0x00
>>> -#define MPIC_INT_IRQ      0x10
>>> -#define MPIC_MSG_IRQ      0xb0
>>> -#define MPIC_MSI_IRQ      0xe0
>>> +#define FSL_MPIC_20_EXT_IRQ      0x00
>>> +#define FSL_MPIC_20_INT_IRQ      0x10
>>> +#define FSL_MPIC_20_MSG_IRQ      0xb0
>>> +#define FSL_MPIC_20_MSI_IRQ      0xe0
>>> /* These are available through separate regions, but
>>>    for simplicity's sake mapped into the same number space */
>>> -#define MPIC_TMR_IRQ      0x100
>>> -#define MPIC_IPI_IRQ      0x104
>>> -
>>> -#define MPIC_GLB_REG_START        0x0
>>> -#define MPIC_GLB_REG_SIZE         0x10F0
>>> -#define MPIC_TMR_REG_START        0x10F0
>>> -#define MPIC_TMR_REG_SIZE         0x220
>>> -#define MPIC_SRC_REG_START        0x10000
>>> -#define MPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
>>> -#define MPIC_CPU_REG_START        0x20000
>>> -#define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>>> +#define FSL_MPIC_20_TMR_IRQ      0x100
>>> +#define FSL_MPIC_20_IPI_IRQ      0x104
>>>
>>> /*
>>>  * Block Revision Register1 (BRR1): QEMU does not fully emulate
>>> @@ -129,6 +116,7 @@ enum {
>>> #define FREP_VID_SHIFT     0
>>>
>>> #define VID_REVISION_1_2   2
>>> +#define VID_REVISION_1_3   3
>>>
>>> #define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
>>>
>>> @@ -205,10 +193,11 @@ typedef struct IRQ_dst_t {
>>> } IRQ_dst_t;
>>>
>>> typedef struct OpenPICState {
>>> -    PCIDevice pci_dev;
>>> +    SysBusDevice busdev;
>>>     MemoryRegion mem;
>>>
>>>     /* Behavior control */
>>> +    uint32_t model;
>>>     uint32_t flags;
>>>     uint32_t nb_irqs;
>>>     uint32_t vid;
>>> @@ -231,15 +220,15 @@ typedef struct OpenPICState {
>>>     IRQ_src_t src[MAX_IRQ];
>>>     /* Local registers per output pin */
>>>     IRQ_dst_t dst[MAX_CPU];
>>> -    int nb_cpus;
>>> +    uint32_t nb_cpus;
>>>     /* Timer registers */
>>>     struct {
>>>         uint32_t ticc;  /* Global timer current count register */
>>>         uint32_t tibc;  /* Global timer base count register */
>>>     } timers[MAX_TMR];
>>> -    int max_irq;
>>> -    int irq_ipi0;
>>> -    int irq_tim0;
>>> +    uint32_t max_irq;
>>> +    uint32_t irq_ipi0;
>>> +    uint32_t irq_tim0;
>>> } OpenPICState;
>>>
>>> static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
>>> @@ -411,9 +400,9 @@ static void openpic_set_irq(void *opaque, int n_IRQ, 
>>> int level)
>>>     openpic_update_irq(opp, n_IRQ);
>>> }
>>>
>>> -static void openpic_reset (void *opaque)
>>> +static void openpic_reset(DeviceState *d)
>>> {
>>> -    OpenPICState *opp = (OpenPICState *)opaque;
>>> +    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));
>>>     int i;
>>>
>>>     opp->glbc = 0x80000000;
>>> @@ -506,7 +495,7 @@ static void openpic_gbl_write(void *opaque, hwaddr 
>>> addr, uint64_t val,
>>>         break;
>>>     case 0x1020: /* GLBC */
>>>         if (val & 0x80000000) {
>>> -            openpic_reset(opp);
>>> +            openpic_reset(&opp->busdev.qdev);
>>>         }
>>>         break;
>>>     case 0x1080: /* VENI */
>>> @@ -971,7 +960,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
>>>         qemu_put_sbe32s(f, &opp->src[i].pending);
>>>     }
>>>
>>> -    qemu_put_sbe32s(f, &opp->nb_cpus);
>>> +    qemu_put_be32s(f, &opp->nb_cpus);
>>>
>>>     for (i = 0; i < opp->nb_cpus; i++) {
>>>         qemu_put_be32s(f, &opp->dst[i].pctp);
>>> @@ -984,8 +973,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
>>>         qemu_put_be32s(f, &opp->timers[i].ticc);
>>>         qemu_put_be32s(f, &opp->timers[i].tibc);
>>>     }
>>> -
>>> -    pci_device_save(&opp->pci_dev, f);
>>> }
>>>
>>> static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
>>> @@ -1020,7 +1007,7 @@ static int openpic_load(QEMUFile* f, void *opaque, 
>>> int version_id)
>>>         qemu_get_sbe32s(f, &opp->src[i].pending);
>>>     }
>>>
>>> -    qemu_get_sbe32s(f, &opp->nb_cpus);
>>> +    qemu_get_be32s(f, &opp->nb_cpus);
>>>
>>>     for (i = 0; i < opp->nb_cpus; i++) {
>>>         qemu_get_be32s(f, &opp->dst[i].pctp);
>>> @@ -1034,7 +1021,7 @@ static int openpic_load(QEMUFile* f, void *opaque, 
>>> int version_id)
>>>         qemu_get_be32s(f, &opp->timers[i].tibc);
>>>     }
>>>
>>> -    return pci_device_load(&opp->pci_dev, f);
>>> +    return 0;
>>> }
>>>
>>> static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
>>> @@ -1048,17 +1035,18 @@ static void openpic_irq_raise(OpenPICState *opp, 
>>> int n_CPU, IRQ_src_t *src)
>>>     }
>>> }
>>>
>>> -qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
>>> -                        qemu_irq **irqs)
>>> +struct memreg {
>>
>> Sorry for not noticing this earlier, but this should be MemReg with
>> also a typedef.
>
> Ok, would you mind a follow-up patch?

OK.

>
>
> Alex
>