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[Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0 |
Date: |
Wed, 9 Jan 2013 16:27:38 +0100 |
When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.
Reviewed-by: Eric Johnson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-mips/translate.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6281e70..d1fc5af 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12657,11 +12657,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env,
DisasContext *ctx, uint32_t opc,
const char *opn = "ldx";
TCGv t0;
- if (rd == 0) {
- MIPS_DEBUG("NOP");
- return;
- }
-
check_dsp(ctx);
t0 = tcg_temp_new();
--
1.7.10.4
- [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 3/8] target-mips: generate a reserved instruction exception on CPU without DSP, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 4/8] target-mips: add unions to access DSP elements, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 8/8] target-mips: implement DSP (d)append sub-class with TCG, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators, Aurelien Jarno, 2013/01/09