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[Qemu-devel] [RFC qom-cpu v2 00/28] CPUState QOM realizefn support


From: Andreas Färber
Subject: [Qemu-devel] [RFC qom-cpu v2 00/28] CPUState QOM realizefn support
Date: Sun, 20 Jan 2013 08:22:23 +0100

Hello,

This series cleans up cpu_init() by moving code to QOM realizefn and initfn.
As a result, the following target CPUs become fully QOM-instantiatable:
arm, microblaze, openrisc, ppc, s390x and unicore32.
The other targets are still in need of model-specific CPU subclasses.

v2 fixes a bug with gdb arm coprocessor registration spotted by Eduardo and
adjusts m68k as well. It also appends patches to move code to initfn.

In response to conceptual questions raised by Eduardo, I'm letting each
target CPU call its parent's realizefn from the start. This requires knowledge
of what the parent does and how we want to interact with its implementation:
To avoid a local_err variable and dedicated error handling, and in light of
ideas to unify reset handling, the parent realizefn is called last.
NB this is not a general QOM'ism, e.g., CPUClass::reset calls it in the middle.

alpha and unicore32 are lacking a full CPUClass::reset implementation.
ppc, sparc and xtensa do not reset as part of cpu_init() today, still
blocking us from moving cpu_reset() into the base CPUState realizefn,
so that it remains empty (and optional) in this series.

Based on a few cleanups sent out for 1.4, but only cris and microblaze are
affected. Patches are strictly target-specific, so for testing arm just the
two target-arm patches can be picked, not strictly depending on patch 1 even.

I'd like to queue this on my qom-cpu-next branch for v1.5 as base for
further series. Still not fully tested but more so.

Available for testing and cherry-picking from:
git://github.com/afaerber/qemu-cpu.git qom-cpu-realize.v2
https://github.com/afaerber/qemu-cpu/commits/qom-cpu-realize.v2

Regards,
Andreas

v1 -> v2:
* arm: Register cp with gdb from realizefn, spotted by Eduardo.
* m68k: Perform gdb init from realizefn as well.
* Introduce a no-op realizefn at CPU level and call it from each target's 
realizefn.
* i386: Avoid error handling regression for APIC.
* s390x: Move cpu_reset() from initfn to realizefn.
* Stylistic changes (e.g., white line after NULL-errp 
object_property_set_bool())
* Appended patches moving TCG initialization from cpu_*_init() to initfn.

Changes from sh4 subclasses series:
* Adopted QOM realizefn signature, dropped error.h inclusion.

Cc: Anthony Liguori <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Igor Mammedov <address@hidden>
Cc: Richard Henderson <address@hidden> (alpha, s390)
Cc: Peter Maydell <address@hidden> (arm)
Cc: Edgar E. Iglesias <address@hidden> (cris, microblaze)
Cc: Peter C. Crosthwaite <address@hidden> (microblaze)
Cc: Michael Walle <address@hidden> (lm32)
Cc: Aurélien Jarno <address@hidden> (mips, sh4)
Cc: Alexander Graf <address@hidden> (ppc, s390)
Cc: qemu-ppc <address@hidden>
Cc: Blue Swirl <address@hidden> (sparc)
Cc: Guan Xuetao <address@hidden> (unicore32)
Cc: Max Filippov <address@hidden> (xtensa)
Cc: Jia Liu <address@hidden> (openrisc)

Andreas Färber (28):
  cpu: Prepare QOM realizefn
  target-alpha: Update AlphaCPU to QOM realizefn
  target-arm: Update ARMCPU to QOM realizefn
  target-i386: Update X86CPU to QOM realizefn
  target-openrisc: Update OpenRISCCPU to QOM realizefn
  target-ppc: Update PowerPCCPU to QOM realizefn
  target-cris: Introduce QOM realizefn for CRISCPU
  target-lm32: Introduce QOM realizefn for LM32CPU
  target-m68k: Introduce QOM realizefn for M68kCPU
  target-microblaze: Introduce QOM realizefn for MicroBlazeCPU
  target-mips: Introduce QOM realizefn for MIPSCPU
  target-s390x: Introduce QOM realizefn for S390CPU
  target-sh4: Introduce QOM realizefn for SuperHCPU
  target-sparc: Introduce QOM realizefn for SPARCCPU
  target-unicore32: Introduce QOM realizefn for UniCore32CPU
  target-xtensa: Introduce QOM realizefn for XtensaCPU
  target-arm: Move TCG initialization to ARMCPU initfn
  target-cris: Move TCG initialization to CRISCPU initfn
  target-lm32: Move TCG initialization to LM32CPU initfn
  target-m68k: Move TCG initialization to M68kCPU initfn
  target-microblaze: Move TCG initialization to MicroBlazeCPU initfn
  target-mips: Move TCG initialization to MIPSCPU initfn
  target-ppc: Move TCG initialization to PowerPCCPU initfn
  target-s390x: Move TCG initialization to S390CPU initfn
  target-sh4: Move TCG initialization to SuperHCPU initfn
  target-sparc: Move TCG initialization to SPARCCPU initfn
  target-unicore32: Move TCG initialization to UniCore32CPU initfn
  target-xtensa: Move TCG initialization to XtensaCPU initfn

 qom/cpu.c                     |    5 +++++
 target-alpha/cpu-qom.h        |    2 ++
 target-alpha/cpu.c            |   21 +++++++++++++++++----
 target-arm/cpu-qom.h          |    3 ++-
 target-arm/cpu.c              |   27 ++++++++++++++++++++-------
 target-arm/cpu.h              |    1 +
 target-arm/helper.c           |   18 +++++++++---------
 target-cris/cpu-qom.h         |    2 ++
 target-cris/cpu.c             |   25 +++++++++++++++++++++++++
 target-cris/cpu.h             |    3 +++
 target-cris/translate.c       |   22 ++++++----------------
 target-cris/translate_v10.c   |    5 +----
 target-i386/cpu-qom.h         |    5 ++---
 target-i386/cpu.c             |   19 +++++++++++++++----
 target-i386/helper.c          |    2 +-
 target-lm32/cpu-qom.h         |    2 ++
 target-lm32/cpu.c             |   22 +++++++++++++++++++++-
 target-lm32/helper.c          |    8 +-------
 target-m68k/cpu-qom.h         |    2 ++
 target-m68k/cpu.c             |   23 +++++++++++++++++++++++
 target-m68k/cpu.h             |    1 +
 target-m68k/helper.c          |   21 ++++++++++-----------
 target-microblaze/cpu-qom.h   |    2 ++
 target-microblaze/cpu.c       |   21 +++++++++++++++++++++
 target-microblaze/cpu.h       |    1 +
 target-microblaze/translate.c |   16 ++++++----------
 target-mips/cpu-qom.h         |    2 ++
 target-mips/cpu.c             |   19 +++++++++++++++++++
 target-mips/cpu.h             |    1 +
 target-mips/translate.c       |    8 ++++----
 target-openrisc/cpu.c         |   13 ++++++++++---
 target-openrisc/cpu.h         |    4 ++--
 target-ppc/cpu-qom.h          |    2 ++
 target-ppc/translate_init.c   |   21 +++++++++++++--------
 target-s390x/cpu-qom.h        |    2 ++
 target-s390x/cpu.c            |   21 ++++++++++++++++++++-
 target-s390x/helper.c         |    9 ++-------
 target-sh4/cpu-qom.h          |    2 ++
 target-sh4/cpu.c              |   19 +++++++++++++++++++
 target-sh4/cpu.h              |    1 +
 target-sh4/translate.c        |    8 ++++----
 target-sparc/cpu-qom.h        |    2 ++
 target-sparc/cpu.c            |   25 ++++++++++++++++++++-----
 target-unicore32/cpu-qom.h    |    3 +++
 target-unicore32/cpu.c        |   26 ++++++++++++++++++++++++++
 target-unicore32/helper.c     |    7 +------
 target-xtensa/cpu-qom.h       |    2 ++
 target-xtensa/cpu.c           |   21 +++++++++++++++++++++
 target-xtensa/cpu.h           |    1 +
 target-xtensa/helper.c        |   16 +++-------------
 50 Dateien geändert, 383 Zeilen hinzugefügt(+), 131 Zeilen entfernt(-)

-- 
1.7.10.4




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