[Qemu-devel] [RFC PATCH 1/2] q35: Fix PIC-mode interrupt setup

[Alex Williamson]

We're initializing the ICH9 PIRQn registers with the IRQEN bit set,
which actuall makes them operate in APIC mode rather than PIC mode
(see 13.1.17 & 13.1.9).  AFAICT, the system boots up in PIC mode and
trying to make use of APIC IRQs in boot ROMs does not work.  Fix this
to use the ISA compatible IRQs.

Signed-off-by: Alex Williamson <address@hidden>
---
 src/pciinit.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/pciinit.c b/src/pciinit.c
index a406bbd..857e8af 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -143,11 +143,9 @@ void mch_isa_bridge_init(struct pci_device *dev, void *arg)
         /* activate irq remapping in LPC */
 
         /* PIRQ[A-D] routing */
-        pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i,
-                          irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+        pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
         /* PIRQ[E-H] routing */
-        pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i,
-                          irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+        pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
     }
     outb(elcr[0], ICH9_LPC_PORT_ELCR1);
     outb(elcr[1], ICH9_LPC_PORT_ELCR2);