qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] [PATCH] qapi/x86: add control registers to query-cpus


From: peter
Subject: [Qemu-devel] [PATCH] qapi/x86: add control registers to query-cpus
Date: Wed, 23 Jan 2013 16:45:50 -0500

From: Peter Feiner <address@hidden>

Adds control registers that govern virtual address translation to query-cpus.

Given these registers and the guest's physical memory, which can be obtained
with dump-guest-memory, a client can perform virtual-to-physical translations.
This is useful for debugging and introspection.

Signed-off-by: Peter Feiner <address@hidden>
---
 cpus.c           |    8 ++++++++
 qapi-schema.json |   10 ++++++++++
 2 files changed, 18 insertions(+)

diff --git a/cpus.c b/cpus.c
index a4390c3..e9cc620 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1224,6 +1224,14 @@ CpuInfoList *qmp_query_cpus(Error **errp)
 #if defined(TARGET_I386)
         info->value->has_pc = true;
         info->value->pc = env->eip + env->segs[R_CS].base;
+        info->value->has_cr0 = true;
+        info->value->cr0 = env->cr[0];
+        info->value->has_cr3 = true;
+        info->value->cr3 = env->cr[3];
+        info->value->has_cr4 = true;
+        info->value->cr4 = env->cr[4];
+        info->value->has_efer = true;
+        info->value->efer = env->efer;
 #elif defined(TARGET_PPC)
         info->value->has_nip = true;
         info->value->nip = env->nip;
diff --git a/qapi-schema.json b/qapi-schema.json
index 6d7252b..80df503 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -569,6 +569,15 @@
 #                If the target is Sparc, this is the PC component of the
 #                instruction pointer.
 #
+# @cr0: #optional If the target is i386 or x86_64, this is the CR1 register.
+#
+# @cr3: #optional If the target is i386 or x86_64, this is the CR3 register.
+#
+# @cr4: #optional If the target is i386 or x86_64, this is the CR4 register.
+#
+# @efer: #optional If the target is i386 or x86_64, this is the "efer"
+#                   (extended features) register.
+#
 # @nip: #optional If the target is PPC, the instruction pointer
 #
 # @npc: #optional If the target is Sparc, the NPC component of the instruction
@@ -585,6 +594,7 @@
 ##
 { 'type': 'CpuInfo',
   'data': {'CPU': 'int', 'current': 'bool', 'halted': 'bool', '*pc': 'int',
+           '*cr0': 'int', '*cr3': 'int', '*cr4': 'int', '*efer', 'int',
            '*nip': 'int', '*npc': 'int', '*PC': 'int', 'thread_id': 'int'} }
 
 ##
-- 
1.7.10.4




reply via email to

[Prev in Thread] Current Thread [Next in Thread]