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[Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow |
Date: |
Wed, 23 Jan 2013 20:03:15 -0800 |
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 91 +++++++++++++++++++++++++------------------------
1 file changed, 46 insertions(+), 45 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index be8d3a3..df2cb3d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1069,44 +1069,6 @@ static void gen_do_setcc(TCGv reg, struct CCPrepare cc,
bool inv)
}
}
-static CCPrepare gen_prepare_cc_slow(DisasContext *s, int jcc_op, TCGv reg)
-{
- switch(jcc_op) {
- case JCC_O:
- return gen_prepare_eflags_o(s, reg);
- case JCC_B:
- return gen_prepare_eflags_c(s, reg);
- case JCC_Z:
- return gen_prepare_eflags_z(s, reg);
- case JCC_BE:
- gen_compute_eflags(s);
- return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
- .mask = CC_Z | CC_C };
- case JCC_S:
- return gen_prepare_eflags_s(s, reg);
- case JCC_P:
- return gen_prepare_eflags_p(s, reg);
- case JCC_L:
- gen_compute_eflags(s);
- if (TCGV_EQUAL(reg, cpu_cc_src)) {
- reg = cpu_tmp0;
- }
- tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
- tcg_gen_xor_tl(reg, reg, cpu_cc_src);
- return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, .mask = CC_S };
- default:
- case JCC_LE:
- gen_compute_eflags(s);
- if (TCGV_EQUAL(reg, cpu_cc_src)) {
- reg = cpu_tmp0;
- }
- tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
- tcg_gen_xor_tl(reg, reg, cpu_cc_src);
- return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
- .mask = CC_S | CC_Z };
- }
-}
-
/* perform a conditional store into register 'reg' according to jump opcode
value 'b'. In the fast case, T0 is guaranted not to be used. */
static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
@@ -1119,11 +1081,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b,
TCGv reg)
jcc_op = (b >> 1) & 7;
switch (s->cc_op) {
- /* we optimize relational operators for the cmp/jcc case */
- case CC_OP_SUBB:
- case CC_OP_SUBW:
- case CC_OP_SUBL:
- case CC_OP_SUBQ:
+ case CC_OP_SUBB ... CC_OP_SUBQ:
+ /* We optimize relational operators for the cmp/jcc case. */
size = s->cc_op - CC_OP_SUBB;
switch (jcc_op) {
case JCC_BE:
@@ -1154,8 +1113,50 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b,
TCGv reg)
default:
slow_jcc:
- /* gen_prepare_cc_slow actually generates good code for JC, JZ and JS
*/
- cc = gen_prepare_cc_slow(s, jcc_op, reg);
+ /* This actually generates good code for JC, JZ and JS. */
+ switch (jcc_op) {
+ case JCC_O:
+ cc = gen_prepare_eflags_o(s, reg);
+ break;
+ case JCC_B:
+ cc = gen_prepare_eflags_c(s, reg);
+ break;
+ case JCC_Z:
+ cc = gen_prepare_eflags_z(s, reg);
+ break;
+ case JCC_BE:
+ gen_compute_eflags(s);
+ cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
+ .mask = CC_Z | CC_C };
+ break;
+ case JCC_S:
+ cc = gen_prepare_eflags_s(s, reg);
+ break;
+ case JCC_P:
+ cc = gen_prepare_eflags_p(s, reg);
+ break;
+ case JCC_L:
+ gen_compute_eflags(s);
+ if (TCGV_EQUAL(reg, cpu_cc_src)) {
+ reg = cpu_tmp0;
+ }
+ tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
+ tcg_gen_xor_tl(reg, reg, cpu_cc_src);
+ cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
+ .mask = CC_S };
+ break;
+ default:
+ case JCC_LE:
+ gen_compute_eflags(s);
+ if (TCGV_EQUAL(reg, cpu_cc_src)) {
+ reg = cpu_tmp0;
+ }
+ tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
+ tcg_gen_xor_tl(reg, reg, cpu_cc_src);
+ cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
+ .mask = CC_S | CC_Z };
+ break;
+ }
break;
}
--
1.7.11.7
- [Qemu-devel] [PATCH 30/57] target-i386: use CCPrepare to generate conditional jumps, (continued)
- [Qemu-devel] [PATCH 30/57] target-i386: use CCPrepare to generate conditional jumps, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 44/57] target-i386: Decode the VEX prefixes, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 43/57] target-i386: Tidy prefix parsing, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 42/57] target-i386: Make helper_cc_compute_all const, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 53/57] target-i386: Implement RORX, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 55/57] target-i386: Use clz/ctz for bsf/bsr helpers, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 54/57] target-i386: Implement ADX extension, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 56/57] target-i386: Simplify bsf/bsr flags computation, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 57/57] target-i386: Implement tzcnt and fix lzcnt, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 33/57] target-i386: introduce gen_cmovcc1, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow,
Richard Henderson <=
- [Qemu-devel] [PATCH 40/57] target-i386: Use CC_SRC2 for ADC and SBB, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 49/57] target-i386: Implement BZHI, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 39/57] target-i386: optimize flags checking after sub using CC_SRC2, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 36/57] target-i386: use gen_op for cmps/scas, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 48/57] target-i386: Implement BLSR, BLSMSK, BLSI, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT, Richard Henderson, 2013/01/23