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[Qemu-devel] [PATCH 50/57] target-i386: Implement MULX
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 50/57] target-i386: Implement MULX |
Date: |
Wed, 23 Jan 2013 20:03:34 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/helper.h | 1 +
target-i386/int_helper.c | 7 +++++++
target-i386/translate.c | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 44 insertions(+)
diff --git a/target-i386/helper.h b/target-i386/helper.h
index aa313bd..b1bae6c 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -18,6 +18,7 @@ DEF_HELPER_2(imulq_EAX_T0, void, env, tl)
DEF_HELPER_3(imulq_T0_T1, tl, env, tl, tl)
DEF_HELPER_2(divq_EAX, void, env, tl)
DEF_HELPER_2(idivq_EAX, void, env, tl)
+DEF_HELPER_FLAGS_2(umulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
#endif
DEF_HELPER_2(aam, void, env, int)
diff --git a/target-i386/int_helper.c b/target-i386/int_helper.c
index 84b812d..4ec8cb7 100644
--- a/target-i386/int_helper.c
+++ b/target-i386/int_helper.c
@@ -385,6 +385,13 @@ void helper_mulq_EAX_T0(CPUX86State *env, target_ulong t0)
CC_SRC = r1;
}
+target_ulong helper_umulh(target_ulong t0, target_ulong t1)
+{
+ uint64_t h, l;
+ mulu64(&l, &h, t0, t1);
+ return h;
+}
+
void helper_imulq_EAX_T0(CPUX86State *env, target_ulong t0)
{
uint64_t r0, r1;
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 46e7b24..dc43ccf 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4099,6 +4099,42 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
set_cc_op(s, CC_OP_BMILGB + ot);
break;
+ case 0x3f6: /* mulx By, Gy, rdx, Ey */
+ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
+ || !(s->prefix & PREFIX_VEX)
+ || s->vex_l != 0) {
+ goto illegal_op;
+ }
+ ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
+#ifdef TARGET_X86_64
+ if (s->dflag == 2) {
+ tcg_gen_mov_tl(cpu_T[1], cpu_regs[R_EDX]);
+ tcg_gen_mul_tl(cpu_regs[s->vex_v], cpu_T[0], cpu_T[1]);
+ gen_helper_umulh(cpu_regs[reg], cpu_T[0], cpu_T[1]);
+ } else
+#endif
+ {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+#ifdef TARGET_X86_64
+ tcg_gen_ext32u_i64(t0, cpu_T[0]);
+ tcg_gen_ext32u_i64(t1, cpu_regs[R_EDX]);
+#else
+ tcg_gen_extu_i32_i64(t0, cpu_T[0]);
+ tcg_gen_extu_i32_i64(t0, cpu_regs[R_EDX]);
+#endif
+ tcg_gen_mul_i64(t0, t0, t1);
+ tcg_gen_trunc_i64_tl(cpu_T[0], t0);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_trunc_i64_tl(cpu_T[1], t0);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ gen_op_mov_reg_T0(OT_LONG, s->vex_v);
+ gen_op_mov_reg_T1(OT_LONG, reg);
+ }
+ break;
+
case 0x0f3:
case 0x1f3:
case 0x2f3:
--
1.7.11.7
- [Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow, (continued)
- [Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 40/57] target-i386: Use CC_SRC2 for ADC and SBB, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 49/57] target-i386: Implement BZHI, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 39/57] target-i386: optimize flags checking after sub using CC_SRC2, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 36/57] target-i386: use gen_op for cmps/scas, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 48/57] target-i386: Implement BLSR, BLSMSK, BLSI, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 38/57] target-i386: Update cc_op before TCG branches, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 50/57] target-i386: Implement MULX,
Richard Henderson <=
- [Qemu-devel] [PATCH 45/57] target-i386: Implement MOVBE, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 32/57] target-i386: cleanup temporary macros for CCPrepare, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 37/57] target-i386: introduce gen_jcc1_noeob, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 52/57] target-i386: Implement SHLX, SARX, SHRX, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 20/57] target-i386: Move CC discards to set_cc_op, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 21/57] target-i386: do not call helper to compute ZF/SF, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 26/57] target-i386: optimize setle, Richard Henderson, 2013/01/24
- [Qemu-devel] [PATCH 22/57] target-i386: use inverted setcond when computing NS or NZ, Richard Henderson, 2013/01/24
- [Qemu-devel] [PATCH 24/57] target-i386: change gen_setcc_slow_T0 to gen_setcc_slow, Richard Henderson, 2013/01/24