[Qemu-devel] [RESEND PATCH v2 1/2] seabios q35: Enable all PIRQn IRQs at startup

[Alex Williamson]

We seem to use the IRQEN bit of the PIRQn registers interchangeably
to select APIC mode or to disable an IRQ.  I can't decide if we're
intending to disable the IRQ or select APIC mode here, but in either
case it prevents PIC mode assigned devices from working.  When seabios
writes IRQEN to these registers, qemu interprets that as APIC mode,
so while the boot ROM driver is waiting for an interrupt on ISA
compatible IRQ 10 or 11, KVM is injecting interrupts to APIC pins
16 - 23.  Devices on the root bus use PIRQE:H while the root ports
use PIRQA:D.  Enable them all so we don't limit where we support boot
ROMs.  The guest will later disable unused IRQs with the ACPI _DIS
method.

Signed-off-by: Alex Williamson <address@hidden>
---
 src/pciinit.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/pciinit.c b/src/pciinit.c
index 1d34653..05c0fe8 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -143,11 +143,9 @@ void mch_isa_bridge_setup(struct pci_device *dev, void 
*arg)
         /* activate irq remapping in LPC */
 
         /* PIRQ[A-D] routing */
-        pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i,
-                          irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+        pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
         /* PIRQ[E-H] routing */
-        pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i,
-                          irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+        pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
     }
     outb(elcr[0], ICH9_LPC_PORT_ELCR1);
     outb(elcr[1], ICH9_LPC_PORT_ELCR2);