[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 29/47] ppc405_uc: Pass PowerPCCPU to ppc40x_{core, c
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [PATCH 29/47] ppc405_uc: Pass PowerPCCPU to ppc40x_{core, chip, system}_reset() |
Date: |
Sat, 16 Feb 2013 16:45:24 +0100 |
Prepares for changing cpu_interrupt() argument to CPUState.
Signed-off-by: Andreas Färber <address@hidden>
Acked-by: Alexander Graf <address@hidden>
---
hw/ppc.c | 12 ++++++------
hw/ppc.h | 6 +++---
hw/ppc405_uc.c | 16 ++++++++++------
3 Dateien geändert, 19 Zeilen hinzugefügt(+), 15 Zeilen entfernt(-)
diff --git a/hw/ppc.c b/hw/ppc.c
index 6053bd5..8cfb84f 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -300,20 +300,20 @@ static void ppc40x_set_irq(void *opaque, int pin, int
level)
if (level) {
LOG_IRQ("%s: reset the PowerPC system\n",
__func__);
- ppc40x_system_reset(env);
+ ppc40x_system_reset(cpu);
}
break;
case PPC40x_INPUT_RESET_CHIP:
if (level) {
LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
- ppc40x_chip_reset(env);
+ ppc40x_chip_reset(cpu);
}
break;
case PPC40x_INPUT_RESET_CORE:
/* XXX: TODO: update DBSR[MRR] */
if (level) {
LOG_IRQ("%s: reset the PowerPC core\n", __func__);
- ppc40x_core_reset(env);
+ ppc40x_core_reset(cpu);
}
break;
case PPC40x_INPUT_CINT:
@@ -1011,13 +1011,13 @@ static void cpu_4xx_wdt_cb (void *opaque)
/* No reset */
break;
case 0x1: /* Core reset */
- ppc40x_core_reset(env);
+ ppc40x_core_reset(cpu);
break;
case 0x2: /* Chip reset */
- ppc40x_chip_reset(env);
+ ppc40x_chip_reset(cpu);
break;
case 0x3: /* System reset */
- ppc40x_system_reset(env);
+ ppc40x_system_reset(cpu);
break;
}
}
diff --git a/hw/ppc.h b/hw/ppc.h
index ee0cd16..acaf0d6 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -58,9 +58,9 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t
freq,
unsigned int decr_excp);
/* Embedded PowerPC reset */
-void ppc40x_core_reset (CPUPPCState *env);
-void ppc40x_chip_reset (CPUPPCState *env);
-void ppc40x_system_reset (CPUPPCState *env);
+void ppc40x_core_reset(PowerPCCPU *cpu);
+void ppc40x_chip_reset(PowerPCCPU *cpu);
+void ppc40x_system_reset(PowerPCCPU *cpu);
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
extern CPUWriteMemoryFunc * const PPC_io_write[];
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index c96d103..d8cbe87 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -1770,8 +1770,9 @@ static void ppc405_mal_init(CPUPPCState *env, qemu_irq
irqs[4])
/*****************************************************************************/
/* SPR */
-void ppc40x_core_reset (CPUPPCState *env)
+void ppc40x_core_reset(PowerPCCPU *cpu)
{
+ CPUPPCState *env = &cpu->env;
target_ulong dbsr;
printf("Reset PowerPC core\n");
@@ -1782,8 +1783,9 @@ void ppc40x_core_reset (CPUPPCState *env)
env->spr[SPR_40x_DBSR] = dbsr;
}
-void ppc40x_chip_reset (CPUPPCState *env)
+void ppc40x_chip_reset(PowerPCCPU *cpu)
{
+ CPUPPCState *env = &cpu->env;
target_ulong dbsr;
printf("Reset PowerPC chip\n");
@@ -1795,7 +1797,7 @@ void ppc40x_chip_reset (CPUPPCState *env)
env->spr[SPR_40x_DBSR] = dbsr;
}
-void ppc40x_system_reset (CPUPPCState *env)
+void ppc40x_system_reset(PowerPCCPU *cpu)
{
printf("Reset PowerPC system\n");
qemu_system_reset_request();
@@ -1803,21 +1805,23 @@ void ppc40x_system_reset (CPUPPCState *env)
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
switch ((val >> 28) & 0x3) {
case 0x0:
/* No action */
break;
case 0x1:
/* Core reset */
- ppc40x_core_reset(env);
+ ppc40x_core_reset(cpu);
break;
case 0x2:
/* Chip reset */
- ppc40x_chip_reset(env);
+ ppc40x_chip_reset(cpu);
break;
case 0x3:
/* System reset */
- ppc40x_system_reset(env);
+ ppc40x_system_reset(cpu);
break;
}
}
--
1.7.10.4
- [Qemu-devel] [PATCH 20/47] target-m68k: Move TCG initialization to M68kCPU initfn, (continued)
- [Qemu-devel] [PATCH 20/47] target-m68k: Move TCG initialization to M68kCPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 21/47] target-microblaze: Move TCG initialization to MicroBlazeCPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 16/47] target-xtensa: Introduce QOM realizefn for XtensaCPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 24/47] target-s390x: Move TCG initialization to S390CPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 22/47] target-mips: Move TCG initialization to MIPSCPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 25/47] target-sh4: Move TCG initialization to SuperHCPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 23/47] target-ppc: Move TCG initialization to PowerPCCPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 26/47] target-sparc: Move TCG initialization to SPARCCPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 43/47] spapr_hcall: Replace open-coded CPU loop with qemu_get_cpu(), Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 36/47] cpu: Move running field to CPUState, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 29/47] ppc405_uc: Pass PowerPCCPU to ppc40x_{core, chip, system}_reset(),
Andreas Färber <=
- [Qemu-devel] [PATCH 27/47] target-unicore32: Move TCG initialization to UniCore32CPU initfn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 45/47] target-lm32: Drop unused cpu_lm32_close() prototype, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 30/47] target-m68k: Return M68kCPU from cpu_m68k_init(), Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 47/47] target-i386: Split command line parsing out of cpu_x86_register(), Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 31/47] mcf5206: Pass M68kCPU to mcf5206_init(), Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 46/47] target-i386: Move cpu_x86_init(), Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 33/47] target-m68k: Pass M68kCPU to m68k_set_irq_level(), Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 41/47] e500: Replace open-coded loop with qemu_get_cpu(), Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 35/47] cpu: Move host_tid field to CPUState, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 39/47] cputlb: Pass CPUState to cpu_unlink_tb(), Andreas Färber, 2013/02/16