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[Qemu-devel] [PATCH 21/57] target-i386: do not call helper to compute ZF
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 21/57] target-i386: do not call helper to compute ZF/SF |
Date: |
Tue, 19 Feb 2013 09:39:55 -0800 |
ZF, SF and PF can always be computed from CC_DST except in the
CC_OP_EFLAGS case (and CC_OP_DYNAMIC, which just resolves to CC_OP_EFLAGS
in gen_compute_eflags). Use setcond to compute ZF and SF.
We could also use a table lookup to compute PF.
Reviewed-by: Blue Swirl <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 37 +++++++++++++++++++++++++++++++------
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index a767b50..026fbd6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -900,9 +900,22 @@ static void gen_compute_eflags_p(DisasContext *s, TCGv reg)
/* compute eflags.S to reg */
static void gen_compute_eflags_s(DisasContext *s, TCGv reg)
{
- gen_compute_eflags(s);
- tcg_gen_shri_tl(reg, cpu_cc_src, 7);
- tcg_gen_andi_tl(reg, reg, 1);
+ switch (s->cc_op) {
+ case CC_OP_DYNAMIC:
+ gen_compute_eflags(s);
+ /* FALLTHRU */
+ case CC_OP_EFLAGS:
+ tcg_gen_shri_tl(reg, cpu_cc_src, 7);
+ tcg_gen_andi_tl(reg, reg, 1);
+ break;
+ default:
+ {
+ int size = (s->cc_op - CC_OP_ADDB) & 3;
+ TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
+ tcg_gen_setcondi_tl(TCG_COND_LT, reg, t0, 0);
+ }
+ break;
+ }
}
/* compute eflags.O to reg */
@@ -916,9 +929,21 @@ static void gen_compute_eflags_o(DisasContext *s, TCGv reg)
/* compute eflags.Z to reg */
static void gen_compute_eflags_z(DisasContext *s, TCGv reg)
{
- gen_compute_eflags(s);
- tcg_gen_shri_tl(reg, cpu_cc_src, 6);
- tcg_gen_andi_tl(reg, reg, 1);
+ switch (s->cc_op) {
+ case CC_OP_DYNAMIC:
+ gen_compute_eflags(s);
+ /* FALLTHRU */
+ case CC_OP_EFLAGS:
+ tcg_gen_shri_tl(reg, cpu_cc_src, 6);
+ tcg_gen_andi_tl(reg, reg, 1);
+ break;
+ default:
+ {
+ int size = (s->cc_op - CC_OP_ADDB) & 3;
+ TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, reg, t0, 0);
+ }
+ }
}
static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
--
1.8.1.2
- [Qemu-devel] [PATCH 12/57] target-i386: factor gen_op_set_cc_op/tcg_gen_discard_tl around computing flags, (continued)
- [Qemu-devel] [PATCH 12/57] target-i386: factor gen_op_set_cc_op/tcg_gen_discard_tl around computing flags, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 14/57] target-i386: Introduce set_cc_op, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 55/57] target-i386: Use clz/ctz for bsf/bsr helpers, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 10/57] target-i386: clean up sahf, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 13/57] target-i386: Name the cc_op enumeration, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 11/57] target-i386: use gen_jcc1 to compile loopz, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 07/57] target-i386: move carry computation for inc/dec closer to gen_op_set_cc_op, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 57/57] target-i386: Add CC_OP_CLR, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 29/57] target-i386: introduce gen_prepare_cc, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 21/57] target-i386: do not call helper to compute ZF/SF,
Richard Henderson <=
- [Qemu-devel] [PATCH 53/57] target-i386: Implement RORX, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 15/57] target-i386: Don't clobber s->cc_op in gen_update_cc_op, Richard Henderson, 2013/02/19