[Qemu-devel] [PATCH 2/3] target-i386: convert decimal number to hexadecimal

[liguang]

convert cpu mode definitions family and model number
which were in decimal into hexadecimal, because they
were both composed by code(4-bit) and extend code(4-bit),
so, in hexadecimal, we can view the 2 fields easily.

Signed-off-by: liguang <address@hidden>
---
 target-i386/cpu.c |   28 ++++++++++++++--------------
 1 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ce76055..b92ee73 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -427,7 +427,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "phenom",
         .level = 5,
         .vendor = CPUID_VENDOR_AMD,
-        .family = 16,
+        .family = 0x10,
         .model = 2,
         .stepping = 3,
         .features = PPRO_FEATURES |
@@ -453,7 +453,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "Opteron_G1",
         .level = 5,
         .vendor = CPUID_VENDOR_AMD,
-        .family = 15,
+        .family = 0xf,
         .model = 6,
         .stepping = 1,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -475,7 +475,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "Opteron_G2",
         .level = 5,
         .vendor = CPUID_VENDOR_AMD,
-        .family = 15,
+        .family = 0xf,
         .model = 6,
         .stepping = 1,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -499,7 +499,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "Opteron_G3",
         .level = 5,
         .vendor = CPUID_VENDOR_AMD,
-        .family = 15,
+        .family = 0xf,
         .model = 6,
         .stepping = 1,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -525,7 +525,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "Opteron_G4",
         .level = 0xd,
         .vendor = CPUID_VENDOR_AMD,
-        .family = 21,
+        .family = 0x15,
         .model = 1,
         .stepping = 2,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -555,7 +555,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "Opteron_G5",
         .level = 0xd,
         .vendor = CPUID_VENDOR_AMD,
-        .family = 21,
+        .family = 0x15,
         .model = 2,
         .stepping = 0,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -585,7 +585,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "kvm64",
         .level = 5,
         .vendor = CPUID_VENDOR_INTEL,
-        .family = 15,
+        .family = 0xf,
         .model = 6,
         .stepping = 1,
         /* Missing: CPUID_VME, CPUID_HT */
@@ -620,7 +620,7 @@ static x86_def_t builtin_x86_defs[] = {
         .name = "kvm32",
         .level = 5,
         .vendor = CPUID_VENDOR_INTEL,
-        .family = 15,
+        .family = 0xf,
         .model = 6,
         .stepping = 1,
         .features = PPRO_FEATURES |
@@ -636,7 +636,7 @@ static x86_def_t builtin_x86_defs[] = {
         .level = 10,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 14,
+        .model = 0xe,
         .stepping = 8,
         .features = PPRO_FEATURES | CPUID_VME |
             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
@@ -652,7 +652,7 @@ static x86_def_t builtin_x86_defs[] = {
         .level = 10,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 15,
+        .model = 0xf,
         .stepping = 11,
         .features = PPRO_FEATURES |
             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
@@ -725,7 +725,7 @@ static x86_def_t builtin_x86_defs[] = {
         .level = 5,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 28,
+        .model = 0x1c,
         .stepping = 2,
         .features = PPRO_FEATURES |
             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
@@ -800,7 +800,7 @@ static x86_def_t builtin_x86_defs[] = {
         .level = 11,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 44,
+        .model = 0x2c,
         .stepping = 1,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@@ -820,7 +820,7 @@ static x86_def_t builtin_x86_defs[] = {
         .level = 0xd,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 42,
+        .model = 0x2a,
         .stepping = 1,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@@ -843,7 +843,7 @@ static x86_def_t builtin_x86_defs[] = {
         .level = 0xd,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 60,
+        .model = 0x3c,
         .stepping = 1,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
-- 
1.7.2.5