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Re: [Qemu-devel] [PATCH 1/3] cpu: make CPU_INTERRUPT_RESET available on
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From: |
Anthony Liguori |
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Subject: |
Re: [Qemu-devel] [PATCH 1/3] cpu: make CPU_INTERRUPT_RESET available on all targets |
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Date: |
Tue, 05 Mar 2013 09:38:20 -0600 |
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User-agent: |
Notmuch/0.13.2+93~ged93d79 (http://notmuchmail.org) Emacs/23.3.1 (x86_64-pc-linux-gnu) |
Paolo Bonzini <address@hidden> writes:
> On the x86, some devices need access to the CPU reset pin (INIT#).
> Provide a generic service to do this, using one of the internal
> cpu_interrupt targets. Generalize the PPC-specific code for
> CPU_INTERRUPT_RESET to other targets, and provide a function that
> will raise the interrupt on all CPUs.
>
> Since PPC does not support migration, I picked the value that is
> used on x86, CPU_INTERRUPT_TGT_INT_1. No other arch used to use
> CPU_INTERRUPT_TGT_INT_1.
>
> Signed-off-by: Paolo Bonzini <address@hidden>
This is a very nice approach.
It would still be nice to remove the explicit reset registrations for
the various cpus and instead just call cpu_soft_reset().
I'm not sure "soft" is the best word. This is just a normal CPU reset
but I won't bikeshed over that.
Reviewed-by: Anthony Liguori <address@hidden>
Regards,
Anthony Liguori
> ---
> cpu-exec.c | 24 ++++++++++++++----------
> cpus.c | 9 +++++++++
> include/exec/cpu-all.h | 8 +++++---
> include/sysemu/cpus.h | 1 +
> target-i386/cpu.h | 7 ++++---
> 5 files changed, 33 insertions(+), 16 deletions(-)
>
> diff --git a/cpu-exec.c b/cpu-exec.c
> index 9092145..e48bb6c 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -300,19 +300,26 @@ int cpu_exec(CPUArchState *env)
> }
> #endif
> #if defined(TARGET_I386)
> -#if !defined(CONFIG_USER_ONLY)
> - if (interrupt_request & CPU_INTERRUPT_POLL) {
> - env->interrupt_request &= ~CPU_INTERRUPT_POLL;
> - apic_poll_irq(env->apic_state);
> - }
> -#endif
> if (interrupt_request & CPU_INTERRUPT_INIT) {
> cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
> 0);
> do_cpu_init(x86_env_get_cpu(env));
> env->exception_index = EXCP_HALTED;
> cpu_loop_exit(env);
> - } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
> + }
> +#else
> + if ((interrupt_request & CPU_INTERRUPT_RESET)) {
> + cpu_reset(cpu);
> + }
> +#endif
> +#if defined(TARGET_I386)
> +#if !defined(CONFIG_USER_ONLY)
> + if (interrupt_request & CPU_INTERRUPT_POLL) {
> + env->interrupt_request &= ~CPU_INTERRUPT_POLL;
> + apic_poll_irq(env->apic_state);
> + }
> +#endif
> + if (interrupt_request & CPU_INTERRUPT_SIPI) {
> do_cpu_sipi(x86_env_get_cpu(env));
> } else if (env->hflags2 & HF2_GIF_MASK) {
> if ((interrupt_request & CPU_INTERRUPT_SMI) &&
> @@ -365,9 +372,6 @@ int cpu_exec(CPUArchState *env)
> }
> }
> #elif defined(TARGET_PPC)
> - if ((interrupt_request & CPU_INTERRUPT_RESET)) {
> - cpu_reset(cpu);
> - }
> if (interrupt_request & CPU_INTERRUPT_HARD) {
> ppc_hw_interrupt(env);
> if (env->pending_interrupts == 0)
> diff --git a/cpus.c b/cpus.c
> index c4b021d..665175d 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -405,6 +405,15 @@ void hw_error(const char *fmt, ...)
> abort();
> }
>
> +void cpu_soft_reset(void)
> +{
> + CPUArchState *env;
> +
> + for (env = first_cpu; env; env = env->next_cpu) {
> + cpu_interrupt(env, CPU_INTERRUPT_RESET);
> + }
> +}
> +
> void cpu_synchronize_all_states(void)
> {
> CPUArchState *cpu;
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 249e046..1361d22 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -392,6 +392,9 @@ DECLARE_TLS(CPUArchState *,cpu_single_env);
> /* Debug event pending. */
> #define CPU_INTERRUPT_DEBUG 0x0080
>
> +/* Reset signal. */
> +#define CPU_INTERRUPT_RESET 0x0400
> +
> /* Several target-specific external hardware interrupts. Each target/cpu.h
> should define proper names based on these defines. */
> #define CPU_INTERRUPT_TGT_EXT_0 0x0008
> @@ -406,9 +409,8 @@ DECLARE_TLS(CPUArchState *,cpu_single_env);
> instruction being executed. These, therefore, are not masked while
> single-stepping within the debugger. */
> #define CPU_INTERRUPT_TGT_INT_0 0x0100
> -#define CPU_INTERRUPT_TGT_INT_1 0x0400
> -#define CPU_INTERRUPT_TGT_INT_2 0x0800
> -#define CPU_INTERRUPT_TGT_INT_3 0x2000
> +#define CPU_INTERRUPT_TGT_INT_1 0x0800
> +#define CPU_INTERRUPT_TGT_INT_2 0x2000
>
> /* First unused bit: 0x4000. */
>
> diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h
> index 6502488..87b9829 100644
> --- a/include/sysemu/cpus.h
> +++ b/include/sysemu/cpus.h
> @@ -7,6 +7,7 @@ void resume_all_vcpus(void);
> void pause_all_vcpus(void);
> void cpu_stop_current(void);
>
> +void cpu_soft_reset(void);
> void cpu_synchronize_all_states(void);
> void cpu_synchronize_all_post_reset(void);
> void cpu_synchronize_all_post_init(void);
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 493dda8..73dacdd 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -577,10 +577,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
> #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
> #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
> -#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
> -#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
> -#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3
> +#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
> +#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
>
> +/* CPU_INTERRUPT_RESET acts as the INIT# pin. */
> +#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
>
> typedef enum {
> CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
> --
> 1.8.1.4