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[Qemu-devel] [PATCH] tcg-mips: Implement muls2_i32
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH] tcg-mips: Implement muls2_i32 |
Date: |
Sun, 24 Mar 2013 01:52:26 +0100 |
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/mips/tcg-target.c | 6 ++++++
tcg/mips/tcg-target.h | 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index bd8c858..373c364 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1413,6 +1413,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
#endif
break;
+ case INDEX_op_muls2_i32:
+ tcg_out_opc_reg(s, OPC_MULT, 0, args[2], args[3]);
+ tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
+ tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0);
+ break;
case INDEX_op_mulu2_i32:
tcg_out_opc_reg(s, OPC_MULTU, 0, args[2], args[3]);
tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
@@ -1595,6 +1600,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_add_i32, { "r", "rZ", "rJ" } },
{ INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
+ { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },
{ INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
{ INDEX_op_div_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 0384bd3..6155327 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -87,7 +87,7 @@ typedef enum {
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
-#define TCG_TARGET_HAS_muls2_i32 0
+#define TCG_TARGET_HAS_muls2_i32 1
/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
--
1.7.10.4
- [Qemu-devel] [PATCH] tcg-mips: Implement muls2_i32,
Aurelien Jarno <=