[Qemu-devel] [PATCH v4 00/33] Modernize tcg/ppc64

[Richard Henderson]

Changes v3-v4:

There were two problems, both related to the setcond opcode:

  * The first was pre-existing: the current code gets 32-bit NE wrong,
    failing to ignore the high 32-bits of the register.  This problem
    caused the rest of the patch set to be non-bisectable -- any non-
    trivial change to code generation of the 32-bit opcodes tended to
    expose this.

  * The second was in the setcond rewrite, in that my logic was wrong
    for the signed comparisons.

In the process of tracking all of this down, I split up the setcond
changes into three parts, and dropped the carry-bit optimization part
entirely.  It may still be an improvement for the unsigned comparisons,
but since I have switched to MFOCRF it'll be harder to show a speedup
in practice.

Finally, one extra patch to avoid a regression in code generation when
insertting zero via deposit.

Tested with arm-test, sparc-test, and i386-softmmu nbench.

Tree updated at

  git://github.com/rth7680/qemu.git tcg-ppc64


r~


Richard Henderson (33):
  disas: Disassemble all ppc insns for the host
  tcg-ppc64: Use TCGReg everywhere
  tcg-ppc64: Introduce and use tcg_out_rlw
  tcg-ppc64: Introduce and use tcg_out_ext32u
  tcg-ppc64: Introduce and use tcg_out_shli64
  tcg-ppc64: Introduce and use tcg_out_shri64
  tcg-ppc64: Introduce and use TAI and SAI
  tcg-ppc64: Fix setcond_i32
  tcg-ppc64: Cleanup tcg_out_movi
  tcg-ppc64: Rearrange integer constant constraints
  tcg-ppc64: Improve constant add and sub ops.
  tcg-ppc64: Allow constant first argument to sub
  tcg-ppc64: Tidy or and xor patterns.
  tcg-ppc64: Improve and_i32 with constant
  tcg-ppc64: Improve and_i64 with constant
  tcg-ppc64: Use automatic implementation of ext32u_i64
  tcg-ppc64: Streamline qemu_ld/st insn selection
  tcg-ppc64: Implement rotates
  tcg-ppc64: Implement bswap16 and bswap32
  tcg-ppc64: Implement bswap64
  tcg-ppc64: Implement compound logicals
  tcg-ppc64: Handle constant inputs for some compound logicals
  tcg-ppc64: Implement deposit
  tcg-ppc64: Use I constraint for mul
  tcg-ppc64: Cleanup i32 constants to tcg_out_cmp
  tcg-ppc64: Use TCGType throughout compares
  tcg-ppc64: Use MFOCRF instead of MFCR
  tcg-ppc64: Use ISEL for setcond
  tcg-ppc64: Implement movcond
  tcg-ppc64: Use getauxval for ISA detection
  tcg-ppc64: Implement add2/sub2_i64
  tcg-ppc64: Implement mulu2/muls2_i64
  tcg-ppc64: Handle deposit of zero

 configure              |   18 +
 disas.c                |    1 +
 tcg/ppc64/tcg-target.c | 1344 +++++++++++++++++++++++++++++++++---------------
 tcg/ppc64/tcg-target.h |   62 +--
 4 files changed, 968 insertions(+), 457 deletions(-)

-- 
1.8.1.4