Re: [Qemu-devel] [PATCH arm-devs v1 15/15] xilinx_spips: lqspi: Fix byte/misaligned access

[Peter Maydell]

On 3 April 2013 05:33, Peter Crosthwaite <address@hidden> wrote:
> The LQSPI bus attachment supports byte/halfword and misaligned
> accesses. Fixed. Refactored the LQSPI cache to be byte-wise
> instead of word wise accordingly.
>
> Signed-off-by: Peter Crosthwaite <address@hidden>
> ---
>
>  hw/xilinx_spips.c |   31 +++++++++++++++++--------------
>  1 files changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
> index 32d8db8..cb45a9c 100644
> --- a/hw/xilinx_spips.c
> +++ b/hw/xilinx_spips.c
> @@ -160,7 +160,7 @@ typedef struct {
>  typedef struct {
>      XilinxSPIPS parent_obj;
>
> -    uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
> +    uint8_t lqspi_buf[LQSPI_CACHE_SIZE];

Is it really right that this buffer isn't in the vmstate,
by the way?

>      hwaddr lqspi_cached_addr;
>  } XilinxQSPIPS;

-- PMM