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Re: [Qemu-devel] [PATCH arm-devs v1 03/15] xilinx_spips: Inhibit interru
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH arm-devs v1 03/15] xilinx_spips: Inhibit interrupts in LQSPI mode |
Date: |
Mon, 8 Apr 2013 08:52:38 +1000 |
Hi Peter,
On Sat, Apr 6, 2013 at 4:41 AM, Peter Maydell <address@hidden> wrote:
> On 3 April 2013 05:27, Peter Crosthwaite <address@hidden> wrote:
>> The real hardware does not produce interrupts in LQSPI mode. Inhibit
>> generation of interrupts when the LQ_MODE bit is set.
>>
>> Signed-off-by: Peter Crosthwaite <address@hidden>
>> ---
>>
>> hw/xilinx_spips.c | 7 ++++++-
>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>
>> diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
>> index 261d948..a8691d5 100644
>> --- a/hw/xilinx_spips.c
>> +++ b/hw/xilinx_spips.c
>> @@ -204,6 +204,9 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
>>
>> static void xilinx_spips_update_ixr(XilinxSPIPS *s)
>> {
>> + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
>> + return;
>> + }
>> /* These are set/cleared as they occur */
>> s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW
>> |
>> IXR_TX_FIFO_MODE_FAIL);
>> @@ -256,7 +259,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
>> for (i = 0; i < num_effective_busses(s); ++i) {
>> if (!i || s->snoop_state == SNOOP_STRIPING) {
>> if (fifo8_is_empty(&s->tx_fifo)) {
>> - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
>> + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
>> + s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
>> + }
>> xilinx_spips_update_ixr(s);
>> return;
>> } else {
>
> How about the OVERFLOW case just below here, or is that a
> deliberate omission?
>
Deliberate omission. Overflow in LQPSI mode should be impossible as
LQSPI always resets the fifos and does one pop for every push. You
could make this happen if you tried to do non-linear accesses while in
linear mode but this is undefined behaviour (perhaps worthy of a
LOG_GUEST_ERROR on the register access but that's a separate followup
patch).
Regards,
Peter
> -- PMM
>
- [Qemu-devel] [PATCH arm-devs v1 00/15] Xilinx SPIPS fixes round 2, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 01/15] xilinx_spips: seperate SPI and QSPI as two classes, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 02/15] xilinx_spips: Make interrupts clear on read, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 03/15] xilinx_spips: Inhibit interrupts in LQSPI mode, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 04/15] xilinx_spips: Add verbose LQSPI debug output, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 05/15] xilinx_spips: lqspi: Dont trash config register, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 06/15] xilinx_spips: Fix QSPI FIFO size, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 07/15] xilinx_spips: Trash LQ page cache on mode change, Peter Crosthwaite, 2013/04/03