Re: [Qemu-devel] [PATCH] i386 ROR r8/r16 instruction fix

[Richard Henderson]

On 2013-04-15 17:42, Aurelien Jarno wrote:
> On Mon, Apr 15, 2013 at 10:59:15AM +0400, Pavel Dovgaluk wrote:
> > Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the TB.
> >
> > Signed-off-by: Pavel Dovgalyuk <address@hidden>
> > ---
> >   target-i386/translate.c |    1 +
> >   1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/target-i386/translate.c b/target-i386/translate.c
> > index 233f24f..40f891d 100644
> > --- a/target-i386/translate.c
> > +++ b/target-i386/translate.c
> > @@ -1775,6 +1775,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int 
> > op1, int is_right)
> >       if (is_right) {
> >           tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
> >           tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
> > +        tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
> >       } else {
> >           tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
> >           tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
>
> This looks correct to me, though I haven't tested.
>
> Reviewed-by: Aurelien Jarno <address@hidden>
>
> The corresponding code seems to have been changed in commit
> 34d80a55ff8517fd37bcfea5063b9797e2bd9132. I therefore added
> Richard in Cc: for him to comment.

Ah, right.  Presumably this was for x86_64 guest running in 32-bit mode?
Because then its 31 bit logical shift, and the only way there could be garbage 
at the top is if the _tl quantity is 64-bit.

One might hope that the known zero bits optimization that we already have will 
eliminate the extra AND when this is an i386 guest, or x86_64 guest with 64-bit 
rotate...

All that said,

Reviewed-by: Richard Henderson <address@hidden>


r~