Re: [Qemu-devel] Qemu for ARM and MRS/MSR banked registers instructions

[Peter Maydell]

On 16 May 2013 13:15, François Legal <address@hidden> wrote:
> Did anybody pointed out that there may be problems with Qemu decoding these
> MRS/MSR banked registers ?
> In my code, I do several
> mrs     %r0, sp_usr
> mrs     %r0, lr_usr
>
> from SVC mode or IRQ mode, and the result I get is CPSR in r0
>
> I took a look in Qemu -> translate.c and op_helper.c, and it seem there is a
> function to access usr/fiq banked registers (get_user_reg) but the call
> hierarchy for this function is not very clear.

The MSR/MRS to/from banked register instructions are for ARMv7VE
only (ie only cores with the Virtualization Extensions). Although
QEMU implements a Cortex-A15 model, our A15 model doesn't support
virtualization, and so we don't implement these virtualization
only instructions.

It's a bug that we don't UNDEF on them, but QEMU's instruction
decoding has generally been rather looser than it should be.

thanks
-- PMM