Re: [Qemu-devel] [PATCH v4 0/3] ARM aarch64 TCG target

[Richard Henderson]

On 05/29/2013 02:04 AM, Claudio Fontana wrote:
> This series implements preliminary support for the ARM aarch64 TCG target.
> 
> Limitations of this initial implementation (TODOs) include:
> 
>  * missing TLB lookup in qemu_ld/st [C helpers always called].
>    An incremental patch, which requires this series, is coming up
>    from colleague Jani Kokkonen to implement this.
>  * most optional opcodes are not implemented yet (only rotation done).
>  * CONFIG_SOFTMMU only
> 
> Tested running on a x86-64 physical machine running Foundation v8,
> running a linux 3.8.0-rc6+ minimal host system based on linaro v8
> image 201301271620 for user space.
> 
> Tested guests: arm v5 test image, i386 FreeDOS test image,
> i386 linux test image, all from qemu-devel testing page.
> Also tested on x86-64/linux built with buildroot,
> and on arm v7/linux built with buildroot as well.
> 
> Changes in v2:
> 
>  * for icache flushing, removed placeholder for old gcc
>  * aligned defines values in the elf aarch64 relocations
>  * added comment in the elf aarch64 relocations
>  * use X16 and X17 as well, they should be safe to use
>  * defined TCG_REG_TMP to TCG_REG_X8
>  * fix relocs and gotos to be more robust during retranslation
>  * removed declarations and assignments on same line
>  * added braces in 'if's even when unnecessary
>  * added comment about COND_NV behaving like COND_AL in aarch64
>  * added comment about no-extend field
>  * remove trampoline for the conditional branches, add CONDBR19
>  * set MAX_CODE_GEN_BUFFER_SIZE for aarch64, matching JUMP26
>  * improved left rotations, by using one less instruction
>  * for setcond_i32/i64 use CSET instead of CSEL
>  * implement andi and subi for working with the stack
>  * do not rely on temp_buf for tcg_set_frame: use stack
>  * remove unused constrained ARM constant
>  * redefine enums with same value to one-another
>  * fix setting of available regs (set all 32 bits)
>  * moved configure patch to after the tcg target in the series
>  * added low level operations useful in preparation of tlb lookup
> 
> Changes in v3:
>  * removed low level operations introduced in v2, will be in separate series
>  * honor 'addend' in patch_reloc, although it's always 0
>  * replace use of 'int' with 'TCGReg' when registers are expected
>  * merge movi32 and movi64 into movi_aux
>  * use 32bit version of the instructions when possible, to save energy/cycles
>  * do not clobber a passed register for INDEX_op_rotl_i32/i64
>  * removed hard coded SP and FP in stack functions, make them params
>  * zero-extend addr_reg for 32bit guests in qemu_ld/st
>  * make use of deposit32 (bitops) in reloc_pc26 and reloc_pc19
>  * never use multiple cases per line in switches even when empty
>  * less pessimistic range checks for instructions
>  * other formatting fixes that fell through the cracks in v2
> 
> Changes in v4:
>  * made move immediate implementation more concise
>  * added comments explaining how the move immediate works
>  * reserve the frame pointer register (FP)
> 
> Claudio Fontana (3):
>   include/elf.h: add aarch64 ELF machine and relocs
>   tcg/aarch64: implement new TCG target for aarch64
>   configure: permit compilation on arm aarch64

Reviewed-by: Richard Henderson <address@hidden>


r~