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[Qemu-devel] [PULL 10/24] xilinx_spips: Fix CTRL register RW bits
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/24] xilinx_spips: Fix CTRL register RW bits |
Date: |
Mon, 3 Jun 2013 17:30:07 +0100 |
From: Peter Crosthwaite <address@hidden>
The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/xilinx_spips.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index ea8a593..3e9e76c 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -56,6 +56,7 @@
#define CLK_PH (1 << 2)
#define CLK_POL (1 << 1)
#define MODE_SEL (1 << 0)
+#define R_CONFIG_RSVD (0x7bf40000)
/* interrupt mechanism */
#define R_INTR_STATUS (0x04 / 4)
@@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
addr >>= 2;
switch (addr) {
case R_CONFIG:
- mask = 0x0002FFFF;
+ mask = ~(R_CONFIG_RSVD | MAN_START_COM);
break;
case R_INTR_STATUS:
ret = s->regs[addr] & IXR_ALL;
@@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
addr >>= 2;
switch (addr) {
case R_CONFIG:
- mask = 0x0002FFFF;
+ mask = ~(R_CONFIG_RSVD | MAN_START_COM);
if (value & MAN_START_COM) {
man_start_com = 1;
}
--
1.7.9.5
- [Qemu-devel] [PULL 00/24] arm-devs queue, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 09/24] xilinx_spips: lqspi: Dont touch config register, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 10/24] xilinx_spips: Fix CTRL register RW bits,
Peter Maydell <=
- [Qemu-devel] [PULL 14/24] xilinx_spips: lqspi: Push more data to tx-fifo, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 24/24] i.MX: Improve EPIT timer code., Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 12/24] xilinx_spips: Debug msgs for Snoop state, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 13/24] xilinx_spips: Multiple debug verbosity levels, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 06/24] xilinx_spips: Trash LQ page cache on mode change, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 15/24] xilinx_spips: lqspi: Fix byte/misaligned access, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 19/24] sd/sdhci:ADMA: fix interrupt, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 23/24] exynos4210.c: register rom_mem for memory migration, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 16/24] sd/sdhci.c: Only reset data_count on new commands, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 03/24] xilinx_spips: Inhibit interrupts in LQSPI mode, Peter Maydell, 2013/06/03