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[Qemu-devel] [PATCH v2 4/5] intc/xilinx_intc: Inhibit write to ISR when
From: |
peter . crosthwaite |
Subject: |
[Qemu-devel] [PATCH v2 4/5] intc/xilinx_intc: Inhibit write to ISR when HIE |
Date: |
Tue, 11 Jun 2013 10:59:55 +1000 |
From: Peter Crosthwaite <address@hidden>
When the Hardware Interrupt Enable (HIE) bit is set, software cannot
change ISR. Add write guard accordingly.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
hw/intc/xilinx_intc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 010b080..e9121cd 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -120,6 +120,11 @@ pic_write(void *opaque, hwaddr addr,
case R_CIE:
p->regs[R_IER] &= ~value; /* Atomic clear ie. */
break;
+ case R_ISR:
+ if ((p->regs[R_MER] & 2)) {
+ break;
+ }
+ /* fallthrough */
default:
if (addr < ARRAY_SIZE(p->regs))
p->regs[addr] = value;
--
1.8.3.rc1.44.gb387c77.dirty
- [Qemu-devel] [PATCH v2 0/5] Xilinx Intc Fixes, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 1/5] microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 2/5] intc/xilinx_intc: Don't clear level sens. IRQs without ACK, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 3/5] intc/xilinx_intc: Handle level interrupt retriggering, peter . crosthwaite, 2013/06/10
- [Qemu-devel] [PATCH v2 4/5] intc/xilinx_intc: Inhibit write to ISR when HIE,
peter . crosthwaite <=
- [Qemu-devel] [PATCH v2 5/5] intc/xilinx_intc: Dont lower IRQ when HIE cleared, peter . crosthwaite, 2013/06/10
- Re: [Qemu-devel] [PATCH v2 0/5] Xilinx Intc Fixes, Edgar E. Iglesias, 2013/06/18