Re: [Qemu-devel] [PATCH] user-exec.c: Set is_write correctly in the ARM cpu_signal_handler()

[Peter Maydell]

On 27 June 2013 17:59, Andreas Färber <address@hidden> wrote:
> Am 04.06.2013 15:31, schrieb Peter Maydell:
>> +    /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
>> +     * later processor; on v5 we will always report this as a read).
>> +     */
>> +    is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
>
> You seem to be relying on v5 and earlier reading zero here - wondering
> if that is true for all implementations (OMAP, PXA, etc.)? Safer and
> closer to the comment might be an explicit check for v6+ if that were
> possible.

The kernel will clear bit 11 if on a v4 or v5 core, eg:
http://lxr.linux.no/#linux+v3.9.7/arch/arm/mm/abort-ev5t.S#L24

As I say in the commit message, v5 hosts are going to be badly
broken (or possibly just hideously inefficient) because of the
unaligned access thing anyway.

thanks
-- PMM