Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer

[Benjamin Herrenschmidt]

On Fri, 2013-07-12 at 12:49 -0500, Anthony Liguori wrote:
> 
> > Unless they are completely broken (and those exist, don't get me wrong,
> > though mostly they are a thing of a past long gone), bridges and busses
> > have no effect on endianness.
> 
> That's simply not true.  There are programmable PCI host bridges that
> support byte swapping.  Some allow this to be done on a per-device basis
> too.

Those bridges are utterly broken and the result of very sick HW design
mind. I've encountered that sort of thing before and the only sane way
to use them is to disable that shit.

If a bridge swaps, it breaks byte order of non-register accesses (FIFO
transfers, DMAs, ...) and hell breaks lose.

Unless you confuse with the byte lane swapping that must occur when
bridging a processor to a bus when the processor changes its bus byte
order.

IE. Some processors (generally older, people have grown clues since
then) that can support dual endian operations had the bad habit of
reversing the location of the low-address and high-address bytes on
their bus (or rather didn't properly reverse LSB/MSB and thus requires
bridges to do it). Such processors do require the bridge to swap the
byte lanes when changing endianness. However I've been told that even
ARM doesn't do that any more.

In any case, even if you want to model a piece of crap like that, you
shouldn't do so by calling the bus "big endian" or "little endian" but
something like a byte lane swap attribute, which more precisely
describes what the bridge is doing. This is not endianness.

> > So I'm not sure what you guys are up to, but from what I read, it's
> > wrong, and the fact at this stage is that your broke IO space (and thus
> > virtio and VGA) on powerpc (including pseries).
> 
> I'm not sure what this patch was trying to do but it was certainly
> wrong.

Right :-)

Ben.