[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH] target-or32: fix masking in openrisc_pic_cpu_ha
From: |
Paolo Bonzini |
Subject: |
Re: [Qemu-devel] [PATCH] target-or32: fix masking in openrisc_pic_cpu_handler() |
Date: |
Sat, 27 Jul 2013 01:07:32 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 |
Il 22/01/2013 16:57, Xi Wang ha scritto:
> A correct mask should be `x & (1 << i)', rather than `x && (1 << i)'.
>
> Also, in C99 signed shift (1 << 31) is undefined behavior, since the
> result exceeds INT_MAX; use 1U instead.
>
> Signed-off-by: Xi Wang <address@hidden>
> ---
> hw/openrisc_pic.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c
> index aaeb9a9..4f6d5a0 100644
> --- a/hw/openrisc_pic.c
> +++ b/hw/openrisc_pic.c
> @@ -26,12 +26,14 @@ static void openrisc_pic_cpu_handler(void *opaque, int
> irq, int level)
> {
> OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
> int i;
> - uint32_t irq_bit = 1 << irq;
> + uint32_t irq_bit;
>
> if (irq > 31 || irq < 0) {
> return;
> }
>
> + irq_bit = 1U << irq;
> +
> if (level) {
> cpu->env.picsr |= irq_bit;
> } else {
> @@ -39,11 +41,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int
> irq, int level)
> }
>
> for (i = 0; i < 32; i++) {
> - if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
> + if ((cpu->env.picsr & (1U << i)) && (cpu->env.picmr & (1U << i))) {
> cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
> } else {
> cpu_reset_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
> - cpu->env.picsr &= ~(1 << i);
> + cpu->env.picsr &= ~(1U << i);
> }
> }
> }
>
Ping.
Paolo
- Re: [Qemu-devel] [PATCH] target-or32: fix masking in openrisc_pic_cpu_handler(),
Paolo Bonzini <=