[Qemu-devel] [PATCH for-next 06/15] tcg-ppc64: Move AREG0 to r31

[Richard Henderson]

Now that AREG0 doesn't need to be a global register, non-conflicting
with the normal frame pointer, move it out of the middle of the set.

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/ppc64/tcg-target.c | 4 ++--
 tcg/ppc64/tcg-target.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 2563253..2b3d1bb 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -166,11 +166,11 @@ static const int tcg_target_callee_save_regs[] = {
     TCG_REG_R24,
     TCG_REG_R25,
     TCG_REG_R26,
-    TCG_REG_R27, /* currently used for the global env */
+    TCG_REG_R27,
     TCG_REG_R28,
     TCG_REG_R29,
     TCG_REG_R30,
-    TCG_REG_R31
+    TCG_REG_R31, /* currently used for the global env */
 };
 
 static inline bool in_range_b(intptr_t disp)
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 48fc6e2..66d0515 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -119,7 +119,7 @@ typedef enum {
 #define TCG_TARGET_HAS_mulu2_i64        1
 #define TCG_TARGET_HAS_muls2_i64        1
 
-#define TCG_AREG0 TCG_REG_R27
+#define TCG_AREG0 TCG_REG_R31
 
 #define TCG_TARGET_EXTEND_ARGS 1
 
-- 
1.8.3.1