Re: [Qemu-devel] [PATCH 1/2] tcg/mips: detect available host instructions at runtime

[Maciej W. Rozycki]

On Thu, 15 Aug 2013, Aurelien Jarno wrote:

> +    /* Probe for MIPS32 instructions. As no subsetting is allowed
> +       by the specification, it is only necessary to probe for one
> +       of the instructions. */
> +#ifndef use_mips32_instructions
> +    got_sigill = 0;
> +    asm volatile(".set push\n"
> +                 ".set mips32\n"
> +                 "mult $zero, $zero\n"
> +                 ".set pop\n"
> +                 : : : );
> +    use_mips32_instructions = !got_sigill;
> +#endif

 Are you sure?  MULT is an ISA I instruction.  Perhaps you meant the 
three-argument MUL?  But that might be slightly usafe as a MIPS32 ISA 
detector because that instruction was also implemented on the earlier NEC 
Vr5500 chips.  By the look at opcodes/mips-opc.c in binutils Vr5500 chips 
implement most, but not all MIPS32 ISA instructions.  So the question is 
-- how close the host has to be?

 The MIPS32 instructions missing from Vr5500 are the EJTAG stuff (DERET 
and SDBBP), JR.HB/JALR.HB (hmm, weird -- these are actually not guaranteed 
to work on all MIPS32 chips either, e.g. the 4Kc didn't support these 
encodings and trapped), SYNC, three-argument MFCx/MTCx instructions (CP0, 
CP2, CP3 register set selection) and two-argument BC2* instructions (extra 
CP2 condition bits).

 All it looks like pretty obscure stuff to me as far as QEMU is concerned, 
so perhaps checking for MUL is good enough.  But I'm not the QEMU expert 
here, so I'm just raising the issue in hope that you or someone else 
knows.

  Maciej