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[Qemu-devel] [PATCH 3/4] tcg-ppc64: Implement muluh, mulsh
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 3/4] tcg-ppc64: Implement muluh, mulsh |
Date: |
Sat, 17 Aug 2013 16:26:45 -0700 |
Using these instead of mulu2 and muls2 lets us avoid having to argument
overlap analysis in the backend. Normal register allocation will DTRT.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 32 +++++++-------------------------
tcg/ppc64/tcg-target.h | 8 ++++----
2 files changed, 11 insertions(+), 29 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 0678de2..939f7cb 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1975,29 +1975,11 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
const TCGArg *args,
}
break;
- case INDEX_op_mulu2_i64:
- case INDEX_op_muls2_i64:
- {
- int oph = (opc == INDEX_op_mulu2_i64 ? MULHDU : MULHD);
- TCGReg outl = args[0], outh = args[1];
- a0 = args[2], a1 = args[3];
-
- if (outl == a0 || outl == a1) {
- if (outh == a0 || outh == a1) {
- outl = TCG_REG_R0;
- } else {
- tcg_out32(s, oph | TAB(outh, a0, a1));
- oph = 0;
- }
- }
- tcg_out32(s, MULLD | TAB(outl, a0, a1));
- if (oph != 0) {
- tcg_out32(s, oph | TAB(outh, a0, a1));
- }
- if (outl != args[0]) {
- tcg_out_mov(s, TCG_TYPE_I64, args[0], outl);
- }
- }
+ case INDEX_op_muluh_i64:
+ tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
default:
@@ -2124,8 +2106,8 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
{ INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
- { INDEX_op_muls2_i64, { "r", "r", "r", "r" } },
- { INDEX_op_mulu2_i64, { "r", "r", "r", "r" } },
+ { INDEX_op_mulsh_i64, { "r", "r", "r" } },
+ { INDEX_op_muluh_i64, { "r", "r", "r" } },
{ -1 },
};
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 0789daf..fa4b9da 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -118,10 +118,10 @@ typedef enum {
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
-#define TCG_TARGET_HAS_mulu2_i64 1
-#define TCG_TARGET_HAS_muls2_i64 1
-#define TCG_TARGET_HAS_muluh_i64 0
-#define TCG_TARGET_HAS_mulsh_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 0
+#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muluh_i64 1
+#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_AREG0 TCG_REG_R27
--
1.8.1.4
- [Qemu-devel] [PATCH 0/4] tcg: Add muluh and mulsh opcodes, Richard Henderson, 2013/08/17
- [Qemu-devel] [PATCH 1/4] tcg: Add muluh and mulsh opcodes, Richard Henderson, 2013/08/17
- [Qemu-devel] [PATCH 2/4] tcg-mips: Implement mulsh, muluh, Richard Henderson, 2013/08/17
- [Qemu-devel] [PATCH 3/4] tcg-ppc64: Implement muluh, mulsh,
Richard Henderson <=
- [Qemu-devel] [PATCH 4/4] tcg: Constant fold div, rem, Richard Henderson, 2013/08/17
- Re: [Qemu-devel] [PATCH 0/4] tcg: Add muluh and mulsh opcodes, Richard Henderson, 2013/08/27