[Qemu-devel] [RFC 0/2] Implement versatile PCI IMAP registers

[Peter Maydell]

This RFC patchset implements the versatile PCI controller's
IMAP registers correctly. These registers deal with the mapping
of the system address space into PCI space, ie they control
what bits of RAM are written to by bus-mastering PCI devices.
(At the moment we just use the system memory space as the
PCI DMA address space, which means that there is always a
flat 1:1 mapping, which is what Linux happens to expect.)

This is an RFC for two reasons:

(1) I needed to add support to the PCI core code for
    "allow this device to respond if its MMIO BARs are
    programmed for address zero", and I'm not sure I did
    this the right way.
(2) since the core code doesn't forbid a PCI device from
    doing a bus-master access back into its own MMIO bars,
    it's possible for a guest to configure the controller into
    a hall-of-mirrors mapping of the PCI and system memory
    spaces into each other such that an access would loop
    infinitely. This will probably result in infinite
    recursion in QEMU in render_memory_region().
    Suggestions for how to avoid this welcome...

thanks
-- PMM

Peter Maydell (2):
  hw/pci: Add PCI capability to allow BARs at 0
  hw/pci-host/versatile: Implement IMAP registers

 hw/pci-host/versatile.c |   72 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/pci/pci.c            |    3 +-
 include/hw/pci/pci.h    |    3 ++
 3 files changed, 77 insertions(+), 1 deletion(-)

-- 
1.7.9.5