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[Qemu-devel] [PATCH v6 06/24] target-arm: Pass DisasContext* to gen_set_
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v6 06/24] target-arm: Pass DisasContext* to gen_set_pc_im() |
Date: |
Tue, 3 Sep 2013 20:12:06 +0100 |
We want gen_set_pc_im() to work for both AArch64 and AArch32, but
to do this we'll need the DisasContext* so we can tell which mode
we're in, so pass it in as a parameter.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5a465fc..4477402 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -904,7 +904,7 @@ DO_GEN_ST(st8)
DO_GEN_ST(st16)
DO_GEN_ST(st32)
-static inline void gen_set_pc_im(target_ulong val)
+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
tcg_gen_movi_i32(cpu_R[15], val);
}
@@ -3419,10 +3419,10 @@ static inline void gen_goto_tb(DisasContext *s, int n,
target_ulong dest)
tb = s->tb;
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
tcg_gen_goto_tb(n);
- gen_set_pc_im(dest);
+ gen_set_pc_im(s, dest);
tcg_gen_exit_tb((uintptr_t)tb + n);
} else {
- gen_set_pc_im(dest);
+ gen_set_pc_im(s, dest);
tcg_gen_exit_tb(0);
}
}
@@ -3551,7 +3551,7 @@ gen_set_condexec (DisasContext *s)
static void gen_exception_insn(DisasContext *s, int offset, int excp)
{
gen_set_condexec(s);
- gen_set_pc_im(s->pc - offset);
+ gen_set_pc_im(s, s->pc - offset);
gen_exception(excp);
s->is_jmp = DISAS_JUMP;
}
@@ -3560,7 +3560,7 @@ static void gen_nop_hint(DisasContext *s, int val)
{
switch (val) {
case 3: /* wfi */
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_WFI;
break;
case 2: /* wfe */
@@ -6337,7 +6337,7 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
if (isread) {
return 1;
}
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_WFI;
return 0;
default:
@@ -6357,7 +6357,7 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tmp64 = tcg_const_i64(ri->resetvalue);
} else if (ri->readfn) {
TCGv_ptr tmpptr;
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
tmp64 = tcg_temp_new_i64();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
@@ -6380,7 +6380,7 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tmp = tcg_const_i32(ri->resetvalue);
} else if (ri->readfn) {
TCGv_ptr tmpptr;
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
tmp = tcg_temp_new_i32();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
@@ -6415,7 +6415,7 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmphi);
if (ri->writefn) {
TCGv_ptr tmpptr = tcg_const_ptr(ri);
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
tcg_temp_free_ptr(tmpptr);
} else {
@@ -6426,7 +6426,7 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
if (ri->writefn) {
TCGv_i32 tmp;
TCGv_ptr tmpptr;
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
tmp = load_reg(s, rt);
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
@@ -8034,7 +8034,7 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
break;
case 0xf:
/* swi */
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_SWI;
break;
default:
@@ -9935,7 +9935,7 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (cond == 0xf) {
/* swi */
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_SWI;
break;
}
@@ -10185,7 +10185,7 @@ static inline void
gen_intermediate_code_internal(ARMCPU *cpu,
gen_set_label(dc->condlabel);
}
if (dc->condjmp || !dc->is_jmp) {
- gen_set_pc_im(dc->pc);
+ gen_set_pc_im(dc, dc->pc);
dc->condjmp = 0;
}
gen_set_condexec(dc);
--
1.7.9.5
- [Qemu-devel] [PATCH v6 17/24] linux-user: Make sure NWFPE code is 32 bit ARM only, (continued)
- [Qemu-devel] [PATCH v6 17/24] linux-user: Make sure NWFPE code is 32 bit ARM only, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 12/24] linux-user: Don't treat AArch64 cpu names specially, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 22/24] configure: Add handling code for AArch64 targets, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 04/24] target-arm: Export cpu_env, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 03/24] target-arm: Extract the disas struct to a header file, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 18/24] linux-user: Implement cpu_set_tls() and cpu_clone_regs() for AArch64, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 13/24] linux-user: Add cpu loop for AArch64, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 07/24] target-arm: Add new AArch64CPUInfo base class and subclasses, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 21/24] linux-user: Add AArch64 support, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 20/24] linux-user: Allow targets to specify a minimum uname release, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 06/24] target-arm: Pass DisasContext* to gen_set_pc_im(),
Peter Maydell <=
- [Qemu-devel] [PATCH v6 19/24] linux-user: Add AArch64 termbits.h definitions, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 11/24] target-arm: Add AArch64 gdbstub support, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 16/24] linux-user: Add signal handling for AArch64, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 10/24] target-arm: Add AArch64 translation stub, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 14/24] linux-user: Add syscall number definitions for AArch64, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 09/24] target-arm: Prepare translation for AArch64 code, Peter Maydell, 2013/09/03
- [Qemu-devel] [PATCH v6 02/24] target-arm: Abstract out load/store from a vaddr in AArch32, Peter Maydell, 2013/09/03