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Re: [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() argument t
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From: |
Jia Liu |
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Subject: |
Re: [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() argument to CPUState |
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Date: |
Wed, 4 Sep 2013 20:49:57 +0800 |
On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <address@hidden> wrote:
> Signed-off-by: Andreas Färber <address@hidden>
> ---
> cputlb.c | 2 +-
> exec.c | 3 +-
> include/exec/cpu-all.h | 3 --
> include/qom/cpu.h | 3 ++
> linux-user/m68k-sim.c | 3 +-
> linux-user/main.c | 80
> ++++++++++++++++++++---------------------
> target-alpha/helper.c | 2 +-
> target-arm/helper.c | 35 ++++++++++++------
> target-arm/translate.c | 2 +-
> target-cris/helper.c | 4 +--
> target-cris/translate.c | 4 +--
> target-cris/translate_v10.c | 12 +++----
> target-i386/seg_helper.c | 8 +++--
> target-lm32/helper.c | 2 +-
> target-lm32/translate.c | 38 ++++++++++----------
> target-m68k/helper.c | 7 ++--
> target-m68k/m68k-semi.c | 2 +-
> target-m68k/translate.c | 4 ++-
> target-microblaze/helper.c | 4 +--
> target-microblaze/translate.c | 51 +++++++++++++++-----------
> target-mips/op_helper.c | 11 ++++--
> target-mips/translate_init.c | 4 ++-
> target-openrisc/interrupt.c | 2 +-
> target-ppc/cpu.h | 2 +-
> target-ppc/excp_helper.c | 48 ++++++++++++-------------
> target-ppc/mmu_helper.c | 54 ++++++++++++++++------------
> target-ppc/translate_init.c | 5 +--
> target-s390x/cc_helper.c | 3 +-
> target-s390x/fpu_helper.c | 4 ++-
> target-s390x/helper.c | 23 +++++++-----
> target-s390x/mem_helper.c | 11 +++---
> target-sh4/helper.c | 21 +++++++----
> target-sh4/op_helper.c | 4 ++-
> target-sparc/int32_helper.c | 2 +-
> target-sparc/int64_helper.c | 2 +-
> target-unicore32/helper.c | 14 +++-----
> target-unicore32/softmmu.c | 13 ++++---
> target-unicore32/translate.c | 28 +++++++++++++--
> target-unicore32/ucf64_helper.c | 3 +-
> translate-all.c | 16 ++++-----
> 40 files changed, 317 insertions(+), 222 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index f8b9566..20a1efe 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -335,7 +335,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1,
> target_ulong addr)
> if (cc->do_unassigned_access) {
> cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
> } else {
> - cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
> + cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
> TARGET_FMT_lx "\n", addr);
> }
> }
> diff --git a/exec.c b/exec.c
> index ffbf4c3..16e3c4d 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -599,9 +599,8 @@ void cpu_single_step(CPUState *cpu, int enabled)
> #endif
> }
>
> -void cpu_abort(CPUArchState *env, const char *fmt, ...)
> +void cpu_abort(CPUState *cpu, const char *fmt, ...)
> {
> - CPUState *cpu = ENV_GET_CPU(env);
> va_list ap;
> va_list ap2;
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index a26d653..0490454 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -359,9 +359,6 @@ int page_check_range(target_ulong start, target_ulong
> len, int flags);
>
> CPUArchState *cpu_copy(CPUArchState *env);
>
> -void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
> - GCC_FMT_ATTR(2, 3);
> -
> /* Flags for use in ENV->INTERRUPT_PENDING.
>
> The numbers assigned here are non-sequential in order to preserve
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 85ba419..0427a71 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -622,6 +622,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
> void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
> void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
>
> +void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
> + GCC_FMT_ATTR(2, 3);
> +
> #ifdef CONFIG_SOFTMMU
> extern const struct VMStateDescription vmstate_cpu_common;
> #else
> diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c
> index d5926ee..1994e40 100644
> --- a/linux-user/m68k-sim.c
> +++ b/linux-user/m68k-sim.c
> @@ -98,6 +98,7 @@ static int translate_openflags(int flags)
> #define ARG(x) tswap32(args[x])
> void do_m68k_simcall(CPUM68KState *env, int nr)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> uint32_t *args;
>
> args = (uint32_t *)(unsigned long)(env->aregs[7] + 4);
> @@ -165,6 +166,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr)
> check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2)));
> break;
> default:
> - cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr);
> + cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr);
> }
> }
> diff --git a/linux-user/main.c b/linux-user/main.c
> index cadefbe..b3b4ff6 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -1351,11 +1351,11 @@ void cpu_loop(CPUPPCState *env)
> /* Just go on */
> break;
> case POWERPC_EXCP_CRITICAL: /* Critical input
> */
> - cpu_abort(env, "Critical interrupt while in user mode. "
> + cpu_abort(cs, "Critical interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_MCHECK: /* Machine check exception
> */
> - cpu_abort(env, "Machine check exception while in user mode. "
> + cpu_abort(cs, "Machine check exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DSI: /* Data storage exception
> */
> @@ -1419,7 +1419,7 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_EXTERNAL: /* External input
> */
> - cpu_abort(env, "External interrupt while in user mode. "
> + cpu_abort(cs, "External interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_ALIGN: /* Alignment exception
> */
> @@ -1513,11 +1513,11 @@ void cpu_loop(CPUPPCState *env)
> }
> break;
> case POWERPC_EXCP_TRAP:
> - cpu_abort(env, "Tried to call a TRAP\n");
> + cpu_abort(cs, "Tried to call a TRAP\n");
> break;
> default:
> /* Should not happen ! */
> - cpu_abort(env, "Unknown program exception (%02x)\n",
> + cpu_abort(cs, "Unknown program exception (%02x)\n",
> env->error_code);
> break;
> }
> @@ -1533,7 +1533,7 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception
> */
> - cpu_abort(env, "Syscall exception while in user mode. "
> + cpu_abort(cs, "Syscall exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_APU: /* Auxiliary processor unavailable
> */
> @@ -1545,23 +1545,23 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_DECR: /* Decrementer exception
> */
> - cpu_abort(env, "Decrementer interrupt while in user mode. "
> + cpu_abort(cs, "Decrementer interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt
> */
> - cpu_abort(env, "Fix interval timer interrupt while in user mode.
> "
> + cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_WDT: /* Watchdog timer interrupt
> */
> - cpu_abort(env, "Watchdog timer interrupt while in user mode. "
> + cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DTLB: /* Data TLB error
> */
> - cpu_abort(env, "Data TLB exception while in user mode. "
> + cpu_abort(cs, "Data TLB exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_ITLB: /* Instruction TLB error
> */
> - cpu_abort(env, "Instruction TLB exception while in user mode. "
> + cpu_abort(cs, "Instruction TLB exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail.
> */
> @@ -1573,37 +1573,37 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ
> */
> - cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
> + cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
> break;
> case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ
> */
> - cpu_abort(env, "Embedded floating-point round IRQ not
> handled\n");
> + cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
> break;
> case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ
> */
> - cpu_abort(env, "Performance monitor exception not handled\n");
> + cpu_abort(cs, "Performance monitor exception not handled\n");
> break;
> case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt
> */
> - cpu_abort(env, "Doorbell interrupt while in user mode. "
> + cpu_abort(cs, "Doorbell interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt
> */
> - cpu_abort(env, "Doorbell critical interrupt while in user mode. "
> + cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_RESET: /* System reset exception
> */
> - cpu_abort(env, "Reset interrupt while in user mode. "
> + cpu_abort(cs, "Reset interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DSEG: /* Data segment exception
> */
> - cpu_abort(env, "Data segment exception while in user mode. "
> + cpu_abort(cs, "Data segment exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_ISEG: /* Instruction segment exception
> */
> - cpu_abort(env, "Instruction segment exception "
> + cpu_abort(cs, "Instruction segment exception "
> "while in user mode. Aborting\n");
> break;
> /* PowerPC 64 with hypervisor mode support */
> case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception
> */
> - cpu_abort(env, "Hypervisor decrementer interrupt "
> + cpu_abort(cs, "Hypervisor decrementer interrupt "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_TRACE: /* Trace exception
> */
> @@ -1613,19 +1613,19 @@ void cpu_loop(CPUPPCState *env)
> break;
> /* PowerPC 64 with hypervisor mode support */
> case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception
> */
> - cpu_abort(env, "Hypervisor data storage exception "
> + cpu_abort(cs, "Hypervisor data storage exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp
> */
> - cpu_abort(env, "Hypervisor instruction storage exception "
> + cpu_abort(cs, "Hypervisor instruction storage exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception
> */
> - cpu_abort(env, "Hypervisor data segment exception "
> + cpu_abort(cs, "Hypervisor data segment exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp
> */
> - cpu_abort(env, "Hypervisor instruction segment exception "
> + cpu_abort(cs, "Hypervisor instruction segment exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_VPU: /* Vector unavailable exception
> */
> @@ -1637,58 +1637,58 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ
> */
> - cpu_abort(env, "Programmable interval timer interrupt "
> + cpu_abort(cs, "Programmable interval timer interrupt "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_IO: /* IO error exception
> */
> - cpu_abort(env, "IO error exception while in user mode. "
> + cpu_abort(cs, "IO error exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_RUNM: /* Run mode exception
> */
> - cpu_abort(env, "Run mode exception while in user mode. "
> + cpu_abort(cs, "Run mode exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_EMUL: /* Emulation trap exception
> */
> - cpu_abort(env, "Emulation trap exception not handled\n");
> + cpu_abort(cs, "Emulation trap exception not handled\n");
> break;
> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error
> */
> - cpu_abort(env, "Instruction fetch TLB exception "
> + cpu_abort(cs, "Instruction fetch TLB exception "
> "while in user-mode. Aborting");
> break;
> case POWERPC_EXCP_DLTLB: /* Data load TLB miss
> */
> - cpu_abort(env, "Data load TLB exception while in user-mode. "
> + cpu_abort(cs, "Data load TLB exception while in user-mode. "
> "Aborting");
> break;
> case POWERPC_EXCP_DSTLB: /* Data store TLB miss
> */
> - cpu_abort(env, "Data store TLB exception while in user-mode. "
> + cpu_abort(cs, "Data store TLB exception while in user-mode. "
> "Aborting");
> break;
> case POWERPC_EXCP_FPA: /* Floating-point assist exception
> */
> - cpu_abort(env, "Floating-point assist exception not handled\n");
> + cpu_abort(cs, "Floating-point assist exception not handled\n");
> break;
> case POWERPC_EXCP_IABR: /* Instruction address breakpoint
> */
> - cpu_abort(env, "Instruction address breakpoint exception "
> + cpu_abort(cs, "Instruction address breakpoint exception "
> "not handled\n");
> break;
> case POWERPC_EXCP_SMI: /* System management interrupt
> */
> - cpu_abort(env, "System management interrupt while in user mode. "
> + cpu_abort(cs, "System management interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_THERM: /* Thermal interrupt
> */
> - cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
> + cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ
> */
> - cpu_abort(env, "Performance monitor exception not handled\n");
> + cpu_abort(cs, "Performance monitor exception not handled\n");
> break;
> case POWERPC_EXCP_VPUA: /* Vector assist exception
> */
> - cpu_abort(env, "Vector assist exception not handled\n");
> + cpu_abort(cs, "Vector assist exception not handled\n");
> break;
> case POWERPC_EXCP_SOFTP: /* Soft patch exception
> */
> - cpu_abort(env, "Soft patch exception not handled\n");
> + cpu_abort(cs, "Soft patch exception not handled\n");
> break;
> case POWERPC_EXCP_MAINT: /* Maintenance exception
> */
> - cpu_abort(env, "Maintenance exception while in user mode. "
> + cpu_abort(cs, "Maintenance exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_STOP: /* stop translation
> */
> @@ -1744,7 +1744,7 @@ void cpu_loop(CPUPPCState *env)
> /* just indicate that signals should be handled asap */
> break;
> default:
> - cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
> + cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
> break;
> }
> process_pending_signals(env);
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index fd4a70c..cd2373c 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -451,7 +451,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
> }
> break;
> default:
> - cpu_abort(env, "Unhandled CPU exception");
> + cpu_abort(cs, "Unhandled CPU exception");
> }
>
> /* Remember where the exception happened. Emulate real hardware in
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 06dd57c..34407a1 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2091,29 +2091,40 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr
> address, int rw,
> /* These should probably raise undefined insn exceptions. */
> void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
> {
> - cpu_abort(env, "v7m_mrs %d\n", reg);
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
> }
>
> uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
> {
> - cpu_abort(env, "v7m_mrs %d\n", reg);
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
> return 0;
> }
>
> void switch_mode(CPUARMState *env, int mode)
> {
> - if (mode != ARM_CPU_MODE_USR)
> - cpu_abort(env, "Tried to switch out of user mode\n");
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + if (mode != ARM_CPU_MODE_USR) {
> + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
> + }
> }
>
> void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
> {
> - cpu_abort(env, "banked r13 write\n");
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "banked r13 write\n");
> }
>
> uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
> {
> - cpu_abort(env, "banked r13 read\n");
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "banked r13 read\n");
> return 0;
> }
>
> @@ -2308,7 +2319,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> do_v7m_exception_exit(env);
> return;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> return; /* Never happens. Keep compiler happy. */
> }
>
> @@ -2433,7 +2444,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> offset = 4;
> break;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> return; /* Never happens. Keep compiler happy. */
> }
> /* High vectors. */
> @@ -3095,6 +3106,8 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env,
> uint32_t mode)
>
> uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> switch (reg) {
> case 0: /* APSR */
> return xpsr_read(env) & 0xf8000000;
> @@ -3125,13 +3138,15 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t
> reg)
> return env->v7m.control;
> default:
> /* ??? For debugging only. */
> - cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
> + cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n",
> reg);
> return 0;
> }
> }
>
> void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> switch (reg) {
> case 0: /* APSR */
> xpsr_write(env, val, 0xf8000000);
> @@ -3192,7 +3207,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg,
> uint32_t val)
> break;
> default:
> /* ??? For debugging only. */
> - cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
> + cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n",
> reg);
> return;
> }
> }
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 0eaec9f..bfbf1c4 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -10104,7 +10104,7 @@ static inline void
> gen_intermediate_code_internal(ARMCPU *cpu,
> if (dc->condjmp) {
> /* FIXME: This can theoretically happen with self-modifying
> code. */
> - cpu_abort(env, "IO on conditional branch instruction");
> + cpu_abort(cs, "IO on conditional branch instruction");
> }
> gen_io_end();
> }
> diff --git a/target-cris/helper.c b/target-cris/helper.c
> index 08b3864..799cd16 100644
> --- a/target-cris/helper.c
> +++ b/target-cris/helper.c
> @@ -89,7 +89,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int rw,
> rw, mmu_idx, 0);
> if (miss) {
> if (cs->exception_index == EXCP_BUSFAULT) {
> - cpu_abort(env,
> + cpu_abort(cs,
> "CRIS: Illegal recursive bus fault."
> "addr=%" VADDR_PRIx " rw=%d\n",
> address, rw);
> @@ -145,7 +145,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
> break;
>
> case EXCP_BUSFAULT:
> - cpu_abort(env, "Unhandled busfault");
> + cpu_abort(cs, "Unhandled busfault");
> break;
>
> default:
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index 90a4394..bf15ed6 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file,
> int line)
> {
> printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
> qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
> - cpu_abort(dc->env, "%s:%d\n", file, line);
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "%s:%d\n", file, line);
> }
>
> static const char *regnames[] =
> @@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext
> *dc, uint32_t addr,
> break;
> }
> default:
> - cpu_abort(dc->env, "Invalid fetch size %d\n", size);
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Invalid fetch size %d\n",
> size);
> break;
> }
> return r;
> diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
> index 0ade05b..734225f 100644
> --- a/target-cris/translate_v10.c
> +++ b/target-cris/translate_v10.c
> @@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
> default:
> LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
> dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled quickimm\n");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled
> quickimm\n");
> break;
> }
> return 2;
> @@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> case 2: tmp = 1; break;
> case 1: tmp = 0; break;
> default:
> - cpu_abort(dc->env, "Unhandled BIAP");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled
> BIAP");
> break;
> }
>
> @@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> default:
> LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
> dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled
> opcode");
> break;
> }
> } else {
> @@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> default:
> LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
> dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled
> opcode");
> break;
> }
> }
> @@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env,
> DisasContext *dc)
> default:
> LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
> dc->pc, size, dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled
> opcode");
> break;
> }
> return insn_len;
> @@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env,
> DisasContext *dc)
> break;
> default:
> LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
> break;
> }
>
> diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
> index d030793..a3ec4dc 100644
> --- a/target-i386/seg_helper.c
> +++ b/target-i386/seg_helper.c
> @@ -95,6 +95,7 @@ static inline void load_seg_vm(CPUX86State *env, int seg,
> int selector)
> static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
> uint32_t *esp_ptr, int dpl)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> int type, index, shift;
>
> #if 0
> @@ -112,11 +113,11 @@ static inline void get_ss_esp_from_tss(CPUX86State
> *env, uint32_t *ss_ptr,
> #endif
>
> if (!(env->tr.flags & DESC_P_MASK)) {
> - cpu_abort(env, "invalid tss");
> + cpu_abort(CPU(cpu), "invalid tss");
> }
> type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
> if ((type & 7) != 1) {
> - cpu_abort(env, "invalid tss type");
> + cpu_abort(CPU(cpu), "invalid tss type");
> }
> shift = type >> 3;
> index = (dpl * 4 + 2) << shift;
> @@ -782,6 +783,7 @@ static void do_interrupt_protected(CPUX86State *env, int
> intno, int is_int,
>
> static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> int index;
>
> #if 0
> @@ -790,7 +792,7 @@ static inline target_ulong get_rsp_from_tss(CPUX86State
> *env, int level)
> #endif
>
> if (!(env->tr.flags & DESC_P_MASK)) {
> - cpu_abort(env, "invalid tss");
> + cpu_abort(CPU(cpu), "invalid tss");
> }
> index = 8 * level + 4;
> if ((index + 7) > env->tr.limit) {
> diff --git a/target-lm32/helper.c b/target-lm32/helper.c
> index daf0f2f..8f2b9fd 100644
> --- a/target-lm32/helper.c
> +++ b/target-lm32/helper.c
> @@ -86,7 +86,7 @@ void lm32_cpu_do_interrupt(CPUState *cs)
> log_cpu_state_mask(CPU_LOG_INT, cs, 0);
> break;
> default:
> - cpu_abort(env, "unhandled exception type=%d\n",
> + cpu_abort(cs, "unhandled exception type=%d\n",
> cs->exception_index);
> break;
> }
> diff --git a/target-lm32/translate.c b/target-lm32/translate.c
> index 2e4951c..532345b 100644
> --- a/target-lm32/translate.c
> +++ b/target-lm32/translate.c
> @@ -422,7 +422,7 @@ static void dec_divu(DisasContext *dc)
> LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
>
> if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
> - cpu_abort(dc->env, "hardware divider is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not
> available\n");
> }
>
> l1 = gen_new_label();
> @@ -500,7 +500,7 @@ static void dec_modu(DisasContext *dc)
> LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
>
> if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
> - cpu_abort(dc->env, "hardware divider is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not
> available\n");
> }
>
> l1 = gen_new_label();
> @@ -521,7 +521,7 @@ static void dec_mul(DisasContext *dc)
> }
>
> if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
> - cpu_abort(dc->env, "hardware multiplier is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware multiplier is
> not available\n");
> }
>
> if (dc->format == OP_FMT_RI) {
> @@ -590,7 +590,7 @@ static void dec_scall(DisasContext *dc)
> } else if (dc->imm5 == 2) {
> LOG_DIS("break\n");
> } else {
> - cpu_abort(dc->env, "invalid opcode\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid opcode\n");
> }
>
> if (dc->imm5 == 7) {
> @@ -647,10 +647,10 @@ static void dec_rcsr(DisasContext *dc)
> case CSR_WP1:
> case CSR_WP2:
> case CSR_WP3:
> - cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid read access
> csr=%x\n", dc->csr);
> break;
> default:
> - cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "read_csr: unknown
> csr=%x\n", dc->csr);
> break;
> }
> }
> @@ -672,7 +672,7 @@ static void dec_sextb(DisasContext *dc)
> LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
>
> if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
> - cpu_abort(dc->env, "hardware sign extender is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is
> not available\n");
> }
>
> tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
> @@ -683,7 +683,7 @@ static void dec_sexth(DisasContext *dc)
> LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
>
> if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
> - cpu_abort(dc->env, "hardware sign extender is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is
> not available\n");
> }
>
> tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
> @@ -710,7 +710,7 @@ static void dec_sl(DisasContext *dc)
> }
>
> if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
> - cpu_abort(dc->env, "hardware shifter is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not
> available\n");
> }
>
> if (dc->format == OP_FMT_RI) {
> @@ -736,7 +736,7 @@ static void dec_sr(DisasContext *dc)
> /* TODO: check r1 == 1 during runtime */
> } else {
> if (dc->imm5 != 1) {
> - cpu_abort(dc->env, "hardware shifter is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter
> is not available\n");
> }
> }
> }
> @@ -764,7 +764,7 @@ static void dec_sru(DisasContext *dc)
> /* TODO: check r1 == 1 during runtime */
> } else {
> if (dc->imm5 != 1) {
> - cpu_abort(dc->env, "hardware shifter is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter
> is not available\n");
> }
> }
> }
> @@ -802,7 +802,7 @@ static void dec_user(DisasContext *dc)
> {
> LOG_DIS("user");
>
> - cpu_abort(dc->env, "user insn undefined\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "user insn undefined\n");
> }
>
> static void dec_wcsr(DisasContext *dc)
> @@ -868,7 +868,7 @@ static void dec_wcsr(DisasContext *dc)
> case CSR_BP3:
> no = dc->csr - CSR_BP0;
> if (dc->env->num_bps <= no) {
> - cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "breakpoint #%i is not
> available\n", no);
> }
> tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
> break;
> @@ -878,16 +878,16 @@ static void dec_wcsr(DisasContext *dc)
> case CSR_WP3:
> no = dc->csr - CSR_WP0;
> if (dc->env->num_wps <= no) {
> - cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "watchpoint #%i is not
> available\n", no);
> }
> tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
> break;
> case CSR_CC:
> case CSR_CFG:
> - cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid write access
> csr=%x\n", dc->csr);
> break;
> default:
> - cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "write_csr unknown
> csr=%x\n", dc->csr);
> break;
> }
> }
> @@ -933,7 +933,7 @@ static void dec_xor(DisasContext *dc)
>
> static void dec_ill(DisasContext *dc)
> {
> - cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "unknown opcode 0x%02x\n",
> dc->opcode);
> }
>
> typedef void (*DecoderInfo)(DisasContext *dc);
> @@ -967,7 +967,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
> LOG_DIS("nr_nops=%d\t", dc->nr_nops);
> dc->nr_nops++;
> if (dc->nr_nops > 4) {
> - cpu_abort(dc->env, "fetching nop sequence\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "fetching nop
> sequence\n");
> }
> }
>
> @@ -1038,7 +1038,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
> dc->nr_nops = 0;
>
> if (pc_start & 3) {
> - cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
> + cpu_abort(cs, "LM32: unaligned PC=%x\n", pc_start);
> }
>
> next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index 219e8b3..5767390 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -132,6 +132,7 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
>
> void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> int flags;
> uint32_t src;
> uint32_t dest;
> @@ -204,7 +205,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
> flags |= CCF_C;
> break;
> default:
> - cpu_abort(env, "Bad CC_OP %d", cc_op);
> + cpu_abort(CPU(cpu), "Bad CC_OP %d", cc_op);
> }
> env->cc_op = CC_OP_FLAGS;
> env->cc_dest = flags;
> @@ -212,6 +213,8 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
>
> void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> +
> switch (reg) {
> case 0x02: /* CACR */
> env->cacr = val;
> @@ -225,7 +228,7 @@ void HELPER(movec)(CPUM68KState *env, uint32_t reg,
> uint32_t val)
> break;
> /* TODO: Implement control registers. */
> default:
> - cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n",
> + cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x =
> 0x%x\n",
> reg, val);
> }
> }
> diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c
> index 2dea3ca..9dffe8d 100644
> --- a/target-m68k/m68k-semi.c
> +++ b/target-m68k/m68k-semi.c
> @@ -461,7 +461,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
> #endif
> return;
> default:
> - cpu_abort(env, "Unsupported semihosting syscall %d\n", nr);
> + cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting
> syscall %d\n", nr);
> result = 0;
> }
> failed:
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index c005e10..bee0d25 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c
> @@ -894,8 +894,10 @@ DISAS_INSN(undef_fpu)
>
> DISAS_INSN(undef)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> +
> gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
> - cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
> + cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
> }
>
> DISAS_INSN(mulw)
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 50aa55a..59c9ad5 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -98,7 +98,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int rw,
> }
>
> if (cs->exception_index == EXCP_MMU) {
> - cpu_abort(env, "recursive faults\n");
> + cpu_abort(cs, "recursive faults\n");
> }
>
> /* TLB miss. */
> @@ -259,7 +259,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> env->sregs[SR_PC] = env->btarget;
> break;
> default:
> - cpu_abort(env, "unhandled exception type=%d\n",
> + cpu_abort(cs, "unhandled exception type=%d\n",
> cs->exception_index);
> break;
> }
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 31eef0f..4471f5a 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -364,7 +364,7 @@ static void dec_pattern(DisasContext *dc)
> }
> break;
> default:
> - cpu_abort(dc->env,
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)),
> "unsupported pattern insn opcode=%x\n", dc->opcode);
> break;
> }
> @@ -438,9 +438,11 @@ static inline void msr_write(DisasContext *dc, TCGv v)
>
> static void dec_msr(DisasContext *dc)
> {
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> TCGv t0, t1;
> unsigned int sr, to, rn;
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + int mem_index = cpu_mmu_index(cs);
>
> sr = dc->imm & ((1 << 14) - 1);
> to = dc->imm & (1 << 14);
> @@ -534,7 +536,7 @@ static void dec_msr(DisasContext *dc)
> tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState,
> shr));
> break;
> default:
> - cpu_abort(dc->env, "unknown mts reg %x\n", sr);
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown mts reg
> %x\n", sr);
> break;
> }
> } else {
> @@ -583,7 +585,7 @@ static void dec_msr(DisasContext *dc)
> cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
> break;
> default:
> - cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
> + cpu_abort(cs, "unknown mfs reg %x\n", sr);
> break;
> }
> }
> @@ -681,7 +683,7 @@ static void dec_mul(DisasContext *dc)
> t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> default:
> - cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown MUL insn %x\n",
> subcode);
> break;
> }
> done:
> @@ -749,9 +751,11 @@ static void dec_barrel(DisasContext *dc)
>
> static void dec_bit(DisasContext *dc)
> {
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> TCGv t0, t1;
> unsigned int op;
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + int mem_index = cpu_mmu_index(cs);
>
> op = dc->ir & ((1 << 9) - 1);
> switch (op) {
> @@ -846,8 +850,8 @@ static void dec_bit(DisasContext *dc)
> tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
> break;
> default:
> - cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
> - dc->pc, op, dc->rd, dc->ra, dc->rb);
> + cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
> + dc->pc, op, dc->rd, dc->ra, dc->rb);
> break;
> }
> }
> @@ -874,7 +878,9 @@ static void dec_imm(DisasContext *dc)
> static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> + int mem_index = cpu_mmu_index(cs);
>
> if (size == 1) {
> tcg_gen_qemu_ld8u(dst, addr, mem_index);
> @@ -883,7 +889,7 @@ static inline void gen_load(DisasContext *dc, TCGv dst,
> TCGv addr,
> } else if (size == 4) {
> tcg_gen_qemu_ld32u(dst, addr, mem_index);
> } else
> - cpu_abort(dc->env, "Incorrect load size %d\n", size);
> + cpu_abort(cs, "Incorrect load size %d\n", size);
> }
>
> static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
> @@ -1026,7 +1032,7 @@ static void dec_load(DisasContext *dc)
> }
> break;
> default:
> - cpu_abort(dc->env, "Invalid reverse size\n");
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse
> size\n");
> break;
> }
> }
> @@ -1093,7 +1099,9 @@ static void dec_load(DisasContext *dc)
> static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> + int mem_index = cpu_mmu_index(cs);
>
> if (size == 1)
> tcg_gen_qemu_st8(val, addr, mem_index);
> @@ -1101,8 +1109,9 @@ static void gen_store(DisasContext *dc, TCGv addr, TCGv
> val,
> tcg_gen_qemu_st16(val, addr, mem_index);
> } else if (size == 4) {
> tcg_gen_qemu_st32(val, addr, mem_index);
> - } else
> - cpu_abort(dc->env, "Incorrect store size %d\n", size);
> + } else {
> + cpu_abort(cs, "Incorrect store size %d\n", size);
> + }
> }
>
> static void dec_store(DisasContext *dc)
> @@ -1188,7 +1197,7 @@ static void dec_store(DisasContext *dc)
> }
> break;
> default:
> - cpu_abort(dc->env, "Invalid reverse size\n");
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse
> size\n");
> break;
> }
>
> @@ -1257,7 +1266,7 @@ static inline void eval_cc(DisasContext *dc, unsigned
> int cc,
> tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
> break;
> default:
> - cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Unknown condition code
> %x.\n", cc);
> break;
> }
> }
> @@ -1701,8 +1710,9 @@ static inline void decode(DisasContext *dc, uint32_t ir)
>
> LOG_DIS("nr_nops=%d\t", dc->nr_nops);
> dc->nr_nops++;
> - if (dc->nr_nops > 4)
> - cpu_abort(dc->env, "fetching nop sequence\n");
> + if (dc->nr_nops > 4) {
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "fetching nop
> sequence\n");
> + }
> }
> /* bit 2 seems to indicate insn type. */
> dc->type_b = ir & (1 << 29);
> @@ -1773,8 +1783,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu,
> TranslationBlock *tb,
> dc->abort_at_next_insn = 0;
> dc->nr_nops = 0;
>
> - if (pc_start & 3)
> - cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
> + if (pc_start & 3) {
> + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
> + }
>
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> #if !SIM_COMPAT
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index dc0c1cc..14f727f 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -1344,6 +1344,7 @@ void helper_mtc0_compare(CPUMIPSState *env,
> target_ulong arg1)
>
> void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> uint32_t val, old;
> uint32_t mask = env->CP0_Status_rw_bitmask;
>
> @@ -1365,7 +1366,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong
> arg1)
> case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
> case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
> case MIPS_HFLAG_KM: qemu_log("\n"); break;
> - default: cpu_abort(env, "Invalid MMU mode!\n"); break;
> + default:
> + cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
> + break;
> }
> }
> }
> @@ -1973,6 +1976,8 @@ static void debug_pre_eret(CPUMIPSState *env)
>
> static void debug_post_eret(CPUMIPSState *env)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> +
> if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
> qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
> env->active_tc.PC, env->CP0_EPC);
> @@ -1984,7 +1989,9 @@ static void debug_post_eret(CPUMIPSState *env)
> case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
> case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
> case MIPS_HFLAG_KM: qemu_log("\n"); break;
> - default: cpu_abort(env, "Invalid MMU mode!\n"); break;
> + default:
> + cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
> + break;
> }
> }
> }
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index c45b1b2..4d90ed5 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -586,6 +586,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const
> mips_def_t *def)
>
> static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> +
> env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
>
> switch (def->mmu_type) {
> @@ -602,7 +604,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t
> *def)
> case MMU_TYPE_R6000:
> case MMU_TYPE_R8000:
> default:
> - cpu_abort(env, "MMU type not supported\n");
> + cpu_abort(CPU(cpu), "MMU type not supported\n");
> }
> }
> #endif /* CONFIG_USER_ONLY */
> diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
> index 64f2ca6..52bcc6e 100644
> --- a/target-openrisc/interrupt.c
> +++ b/target-openrisc/interrupt.c
> @@ -69,7 +69,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
> if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
> env->pc = (cs->exception_index << 8);
> } else {
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> }
> #endif
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 3b03ae6..ea121dd 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -2051,7 +2051,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState
> *env, ppcmas_tlb_t *tlbm)
> }
> }
>
> - cpu_abort(env, "Unknown TLBe: %d\n", id);
> + cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
> return 0;
> }
>
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index 7ced42d..ef67b0e 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -240,7 +240,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> break;
> default:
> /* Should never occur */
> - cpu_abort(env, "Invalid program exception %d. Aborting\n",
> + cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> env->error_code);
> break;
> }
> @@ -300,26 +300,26 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> break;
> }
> /* XXX: TODO */
> - cpu_abort(env, "Debug exception is not implemented yet !\n");
> + cpu_abort(cs, "Debug exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable
> */
> env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> goto store_current;
> case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt
> */
> /* XXX: TODO */
> - cpu_abort(env, "Embedded floating point data exception "
> + cpu_abort(cs, "Embedded floating point data exception "
> "is not implemented yet !\n");
> env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> goto store_next;
> case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt
> */
> /* XXX: TODO */
> - cpu_abort(env, "Embedded floating point round exception "
> + cpu_abort(cs, "Embedded floating point round exception "
> "is not implemented yet !\n");
> env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> goto store_next;
> case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt
> */
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "Performance counter exception is not implemented yet
> !\n");
> goto store_next;
> case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt
> */
> @@ -396,15 +396,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> goto store_next;
> case POWERPC_EXCP_IO: /* IO error exception
> */
> /* XXX: TODO */
> - cpu_abort(env, "601 IO error exception is not implemented yet !\n");
> + cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_RUNM: /* Run mode exception
> */
> /* XXX: TODO */
> - cpu_abort(env, "601 run mode exception is not implemented yet !\n");
> + cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_EMUL: /* Emulation trap exception
> */
> /* XXX: TODO */
> - cpu_abort(env, "602 emulation trap exception "
> + cpu_abort(cs, "602 emulation trap exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error
> */
> @@ -422,7 +422,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> case POWERPC_EXCP_74xx:
> goto tlb_miss_74xx;
> default:
> - cpu_abort(env, "Invalid instruction TLB miss exception\n");
> + cpu_abort(cs, "Invalid instruction TLB miss exception\n");
> break;
> }
> break;
> @@ -441,7 +441,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> case POWERPC_EXCP_74xx:
> goto tlb_miss_74xx;
> default:
> - cpu_abort(env, "Invalid data load TLB miss exception\n");
> + cpu_abort(cs, "Invalid data load TLB miss exception\n");
> break;
> }
> break;
> @@ -527,30 +527,30 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> msr |= env->error_code; /* key bit */
> break;
> default:
> - cpu_abort(env, "Invalid data store TLB miss exception\n");
> + cpu_abort(cs, "Invalid data store TLB miss exception\n");
> break;
> }
> goto store_next;
> case POWERPC_EXCP_FPA: /* Floating-point assist exception
> */
> /* XXX: TODO */
> - cpu_abort(env, "Floating point assist exception "
> + cpu_abort(cs, "Floating point assist exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_DABR: /* Data address breakpoint
> */
> /* XXX: TODO */
> - cpu_abort(env, "DABR exception is not implemented yet !\n");
> + cpu_abort(cs, "DABR exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_IABR: /* Instruction address breakpoint
> */
> /* XXX: TODO */
> - cpu_abort(env, "IABR exception is not implemented yet !\n");
> + cpu_abort(cs, "IABR exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_SMI: /* System management interrupt
> */
> /* XXX: TODO */
> - cpu_abort(env, "SMI exception is not implemented yet !\n");
> + cpu_abort(cs, "SMI exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_THERM: /* Thermal interrupt
> */
> /* XXX: TODO */
> - cpu_abort(env, "Thermal management exception "
> + cpu_abort(cs, "Thermal management exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt
> */
> @@ -558,36 +558,36 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> new_msr |= (target_ulong)MSR_HVB;
> }
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "Performance counter exception is not implemented yet
> !\n");
> goto store_next;
> case POWERPC_EXCP_VPUA: /* Vector assist exception
> */
> /* XXX: TODO */
> - cpu_abort(env, "VPU assist exception is not implemented yet !\n");
> + cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_SOFTP: /* Soft patch exception
> */
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "970 soft-patch exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_MAINT: /* Maintenance exception
> */
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "970 maintenance exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint
> */
> /* XXX: TODO */
> - cpu_abort(env, "Maskable external exception "
> + cpu_abort(cs, "Maskable external exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint
> */
> /* XXX: TODO */
> - cpu_abort(env, "Non maskable external exception "
> + cpu_abort(cs, "Non maskable external exception "
> "is not implemented yet !\n");
> goto store_next;
> default:
> excp_invalid:
> - cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
> + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> break;
> store_current:
> /* save current instruction location */
> @@ -629,7 +629,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> /* Jump to handler */
> vector = env->excp_vectors[excp];
> if (vector == (target_ulong)-1ULL) {
> - cpu_abort(env, "Raised an exception without defined vector %d\n",
> + cpu_abort(cs, "Raised an exception without defined vector %d\n",
> excp);
> }
> vector |= env->excp_prefix;
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index ff70b38..f4dac00 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -746,9 +746,11 @@ static int mmu40x_get_physical_address(CPUPPCState *env,
> mmu_ctx_t *ctx,
>
> void store_40x_sler(CPUPPCState *env, uint32_t val)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> /* XXX: TO BE FIXED */
> if (val != 0x00000000) {
> - cpu_abort(env, "Little-endian regions are not supported by now\n");
> + cpu_abort(CPU(cpu), "Little-endian regions are not supported by
> now\n");
> }
> env->spr[SPR_405_SLER] = val;
> }
> @@ -1344,6 +1346,7 @@ static inline int check_physical(CPUPPCState *env,
> mmu_ctx_t *ctx,
> static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> target_ulong eaddr, int rw, int access_type)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int ret = -1;
> bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
> || (access_type != ACCESS_CODE && msr_dr == 0);
> @@ -1388,17 +1391,17 @@ static int get_physical_address(CPUPPCState *env,
> mmu_ctx_t *ctx,
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_REAL:
> if (real_mode) {
> ret = check_physical(env, ctx, eaddr, rw);
> } else {
> - cpu_abort(env, "PowerPC in real mode do not do any
> translation\n");
> + cpu_abort(CPU(cpu), "PowerPC in real mode do not do any
> translation\n");
> }
> return -1;
> default:
> - cpu_abort(env, "Unknown or invalid MMU model\n");
> + cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n");
> return -1;
> }
> #if 0
> @@ -1543,14 +1546,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
> target_ulong address,
> return -1;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "PowerPC in real mode should never raise "
> + cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> return -1;
> default:
> - cpu_abort(env, "Unknown or invalid MMU model\n");
> + cpu_abort(cs, "Unknown or invalid MMU model\n");
> return -1;
> }
> break;
> @@ -1623,7 +1626,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
> target_ulong address,
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE206:
> booke206_update_mas_tlb_miss(env, address, rw);
> @@ -1635,11 +1638,11 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
> target_ulong address,
> env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
> return -1;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "PowerPC in real mode should never raise "
> + cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> return -1;
> default:
> - cpu_abort(env, "Unknown or invalid MMU model\n");
> + cpu_abort(cs, "Unknown or invalid MMU model\n");
> return -1;
> }
> break;
> @@ -1893,6 +1896,8 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t
> nr, target_ulong value)
> /* TLB management */
> void ppc_tlb_invalidate_all(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> case POWERPC_MMU_SOFT_74xx:
> @@ -1903,11 +1908,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> ppc4xx_tlb_invalidate_all(env);
> break;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
> + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE:
> tlb_flush(env, 1);
> @@ -1927,7 +1932,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> break;
> default:
> /* XXX: TODO */
> - cpu_abort(env, "Unknown MMU model\n");
> + cpu_abort(CPU(cpu), "Unknown MMU model\n");
> break;
> }
> }
> @@ -1935,6 +1940,8 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> {
> #if !defined(FLUSH_ALL_TLBS)
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> addr &= TARGET_PAGE_MASK;
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> @@ -1949,19 +1956,19 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
> target_ulong addr)
> ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
> break;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
> + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE:
> /* XXX: TODO */
> - cpu_abort(env, "BookE MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE206:
> /* XXX: TODO */
> - cpu_abort(env, "BookE 2.06 MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n");
> break;
> case POWERPC_MMU_32B:
> case POWERPC_MMU_601:
> @@ -2002,7 +2009,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
> target_ulong addr)
> #endif /* defined(TARGET_PPC64) */
> default:
> /* XXX: TODO */
> - cpu_abort(env, "Unknown MMU model\n");
> + cpu_abort(CPU(cpu), "Unknown MMU model\n");
> break;
> }
> #else
> @@ -2316,6 +2323,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env,
> target_ulong entry)
> void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> target_ulong val)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppcemb_tlb_t *tlb;
> target_ulong page, end;
>
> @@ -2339,7 +2347,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
> entry,
> * of the ppc or ppc64 one
> */
> if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
> - cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
> + cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u "
> "are not supported (%d)\n",
> tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
> }
> @@ -2348,7 +2356,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
> entry,
> tlb->prot |= PAGE_VALID;
> if (val & PPC4XX_TLBHI_E) {
> /* XXX: TO BE FIXED */
> - cpu_abort(env,
> + cpu_abort(CPU(cpu),
> "Little-endian TLB entries are not supported by
> now\n");
> }
> } else {
> @@ -2544,6 +2552,7 @@ target_ulong helper_440_tlbsx(CPUPPCState *env,
> target_ulong address)
>
> static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg = 0;
> int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >>
> MAS0_ESEL_SHIFT;
> int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK);
> @@ -2553,7 +2562,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
> tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb];
>
> if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) {
> - cpu_abort(env, "we don't support HES yet\n");
> + cpu_abort(CPU(cpu), "we don't support HES yet\n");
> }
>
> return booke206_get_tlbm(env, tlb, ea, esel);
> @@ -2568,6 +2577,7 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t
> pidn, target_ulong pid)
>
> void helper_booke206_tlbwe(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg, tlbn;
> ppcmas_tlb_t *tlb;
> uint32_t size_tlb, size_ps;
> @@ -2621,7 +2631,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
> }
>
> if (msr_gs) {
> - cpu_abort(env, "missing HV implementation\n");
> + cpu_abort(CPU(cpu), "missing HV implementation\n");
> }
> tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |
> env->spr[SPR_BOOKE_MAS3];
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index db5e526..1df82c5 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -4424,6 +4424,7 @@ enum fsl_e500_version {
>
> static void init_proc_e500 (CPUPPCState *env, int version)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg[2];
> uint64_t ivor_mask;
> uint64_t ivpr_mask = 0xFFFF0000ULL;
> @@ -4482,7 +4483,7 @@ static void init_proc_e500 (CPUPPCState *env, int
> version)
> tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT,
> 64);
> break;
> default:
> - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> }
> #endif
> /* Cache sizes */
> @@ -4499,7 +4500,7 @@ static void init_proc_e500 (CPUPPCState *env, int
> version)
> l1cfg0 |= 0x1000000; /* 64 byte cache block size */
> break;
> default:
> - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> }
> gen_spr_BookE206(env, 0x000000DF, tlbncfg);
> /* XXX : not implemented */
> diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
> index d845f20..9e676a5 100644
> --- a/target-s390x/cc_helper.c
> +++ b/target-s390x/cc_helper.c
> @@ -407,6 +407,7 @@ static uint32_t cc_calc_flogr(uint64_t dst)
> static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
> uint64_t src, uint64_t dst, uint64_t vr)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint32_t r = 0;
>
> switch (cc_op) {
> @@ -524,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t
> cc_op,
> break;
>
> default:
> - cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
> + cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op));
> }
>
> HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
> diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
> index 94375b6..3e9c7b2 100644
> --- a/target-s390x/fpu_helper.c
> +++ b/target-s390x/fpu_helper.c
> @@ -80,6 +80,8 @@ static void handle_exceptions(CPUS390XState *env, uintptr_t
> retaddr)
>
> static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> +
> switch (float_compare) {
> case float_relation_equal:
> return 0;
> @@ -90,7 +92,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int
> float_compare)
> case float_relation_unordered:
> return 3;
> default:
> - cpu_abort(env, "unknown return value for float compare\n");
> + cpu_abort(CPU(cpu), "unknown return value for float compare\n");
> }
> }
>
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index 207af52..96f57d2 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -116,6 +116,7 @@ static void trigger_pgm_exception(CPUS390XState *env,
> uint32_t code,
>
> static int trans_bits(CPUS390XState *env, uint64_t mode)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> int bits = 0;
>
> switch (mode) {
> @@ -129,7 +130,7 @@ static int trans_bits(CPUS390XState *env, uint64_t mode)
> bits = 3;
> break;
> default:
> - cpu_abort(env, "unknown asc mode\n");
> + cpu_abort(CPU(cpu), "unknown asc mode\n");
> break;
> }
>
> @@ -474,13 +475,14 @@ static uint64_t get_psw_mask(CPUS390XState *env)
>
> static LowCore *cpu_map_lowcore(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> LowCore *lowcore;
> hwaddr len = sizeof(LowCore);
>
> lowcore = cpu_physical_memory_map(env->psa, &len, 1);
>
> if (len < sizeof(LowCore)) {
> - cpu_abort(env, "Could not map lowcore\n");
> + cpu_abort(CPU(cpu), "Could not map lowcore\n");
> }
>
> return lowcore;
> @@ -578,16 +580,17 @@ static void do_program_interrupt(CPUS390XState *env)
>
> static void do_ext_interrupt(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint64_t mask, addr;
> LowCore *lowcore;
> ExtQueue *q;
>
> if (!(env->psw.mask & PSW_MASK_EXT)) {
> - cpu_abort(env, "Ext int w/o ext mask\n");
> + cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
> }
>
> if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
> - cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
> + cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index);
> }
>
> q = &env->ext_queue[env->ext_index];
> @@ -617,6 +620,7 @@ static void do_ext_interrupt(CPUS390XState *env)
>
> static void do_io_interrupt(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> LowCore *lowcore;
> IOIntQueue *q;
> uint8_t isc;
> @@ -624,7 +628,7 @@ static void do_io_interrupt(CPUS390XState *env)
> int found = 0;
>
> if (!(env->psw.mask & PSW_MASK_IO)) {
> - cpu_abort(env, "I/O int w/o I/O mask\n");
> + cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n");
> }
>
> for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
> @@ -634,7 +638,7 @@ static void do_io_interrupt(CPUS390XState *env)
> continue;
> }
> if (env->io_index[isc] > MAX_IO_QUEUE) {
> - cpu_abort(env, "I/O queue overrun for isc %d: %d\n",
> + cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n",
> isc, env->io_index[isc]);
> }
>
> @@ -681,24 +685,25 @@ static void do_io_interrupt(CPUS390XState *env)
>
> static void do_mchk_interrupt(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint64_t mask, addr;
> LowCore *lowcore;
> MchkQueue *q;
> int i;
>
> if (!(env->psw.mask & PSW_MASK_MCHECK)) {
> - cpu_abort(env, "Machine check w/o mchk mask\n");
> + cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
> }
>
> if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) {
> - cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index);
> + cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
> }
>
> q = &env->mchk_queue[env->mchk_index];
>
> if (q->type != 1) {
> /* Don't know how to handle this... */
> - cpu_abort(env, "Unknown machine check type %d\n", q->type);
> + cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
> }
> if (!(env->cregs[14] & (1 << 28))) {
> /* CRW machine checks disabled */
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 6a79385..cd84337 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -72,6 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
> is_write, int mmu_idx,
> static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
> uint8_t byte)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> hwaddr dest_phys;
> hwaddr len = l;
> void *dest_p;
> @@ -80,7 +81,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l,
> uint64_t dest,
>
> if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
> cpu_stb_data(env, dest, byte);
> - cpu_abort(env, "should never reach here");
> + cpu_abort(CPU(cpu), "should never reach here");
> }
> dest_phys |= dest & ~TARGET_PAGE_MASK;
>
> @@ -94,6 +95,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l,
> uint64_t dest,
> static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
> uint64_t src)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> hwaddr dest_phys;
> hwaddr src_phys;
> hwaddr len = l;
> @@ -104,13 +106,13 @@ static void mvc_fast_memmove(CPUS390XState *env,
> uint32_t l, uint64_t dest,
>
> if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
> cpu_stb_data(env, dest, 0);
> - cpu_abort(env, "should never reach here");
> + cpu_abort(CPU(cpu), "should never reach here");
> }
> dest_phys |= dest & ~TARGET_PAGE_MASK;
>
> if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) {
> cpu_ldub_data(env, src);
> - cpu_abort(env, "should never reach here");
> + cpu_abort(CPU(cpu), "should never reach here");
> }
> src_phys |= src & ~TARGET_PAGE_MASK;
>
> @@ -483,6 +485,7 @@ static uint32_t helper_icm(CPUS390XState *env, uint32_t
> r1, uint64_t address,
> uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1,
> uint64_t addr, uint64_t ret)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint16_t insn = cpu_lduw_code(env, addr);
>
> HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
> @@ -534,7 +537,7 @@ uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc,
> uint64_t v1,
> cc = helper_icm(env, r1, get_address(env, 0, b2, d2), r3);
> } else {
> abort:
> - cpu_abort(env, "EXECUTE on instruction prefix 0x%x not
> implemented\n",
> + cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not
> implemented\n",
> insn);
> }
> return cc;
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index b444da1..7add92d 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -234,15 +234,21 @@ static void update_itlb_use(CPUSH4State * env, int
> itlbnb)
>
> static int itlb_replacement(CPUSH4State * env)
> {
> - if ((env->mmucr & 0xe0000000) == 0xe0000000)
> + SuperHCPU *cpu = sh_env_get_cpu(env);
> +
> + if ((env->mmucr & 0xe0000000) == 0xe0000000) {
> return 0;
> - if ((env->mmucr & 0x98000000) == 0x18000000)
> + }
> + if ((env->mmucr & 0x98000000) == 0x18000000) {
> return 1;
> - if ((env->mmucr & 0x54000000) == 0x04000000)
> + }
> + if ((env->mmucr & 0x54000000) == 0x04000000) {
> return 2;
> - if ((env->mmucr & 0x2c000000) == 0x00000000)
> + }
> + if ((env->mmucr & 0x2c000000) == 0x00000000) {
> return 3;
> - cpu_abort(env, "Unhandled itlb_replacement");
> + }
> + cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
> }
>
> /* Find the corresponding entry in the right TLB
> @@ -498,7 +504,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr
> address, int rw,
> cs->exception_index = 0x100;
> break;
> default:
> - cpu_abort(env, "Unhandled MMU fault");
> + cpu_abort(cs, "Unhandled MMU fault");
> }
> return 1;
> }
> @@ -522,6 +528,7 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr
> addr)
>
> void cpu_load_tlb(CPUSH4State * env)
> {
> + SuperHCPU *cpu = sh_env_get_cpu(env);
> int n = cpu_mmucr_urc(env->mmucr);
> tlb_t * entry = &env->utlb[n];
>
> @@ -551,7 +558,7 @@ void cpu_load_tlb(CPUSH4State * env)
> entry->size = 1024 * 1024; /* 1M */
> break;
> default:
> - cpu_abort(env, "Unhandled load_tlb");
> + cpu_abort(CPU(cpu), "Unhandled load_tlb");
> break;
> }
> entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index b3ce7ba..720a97b 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -58,8 +58,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
> is_write, int mmu_idx,
> void helper_ldtlb(CPUSH4State *env)
> {
> #ifdef CONFIG_USER_ONLY
> + SuperHCPU *cpu = sh_env_get_cpu(env);
> +
> /* XXXXX */
> - cpu_abort(env, "Unhandled ldtlb");
> + cpu_abort(CPU(cpu), "Unhandled ldtlb");
> #else
> cpu_load_tlb(env);
> #endif
> diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
> index f350a90..7c380ba 100644
> --- a/target-sparc/int32_helper.c
> +++ b/target-sparc/int32_helper.c
> @@ -109,7 +109,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
> qemu_system_shutdown_request();
> } else {
> - cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error
> state",
> + cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error
> state",
> cs->exception_index);
> }
> return;
> diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c
> index 1744245..bf24232 100644
> --- a/target-sparc/int64_helper.c
> +++ b/target-sparc/int64_helper.c
> @@ -111,7 +111,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> #endif
> #if !defined(CONFIG_USER_ONLY)
> if (env->tl >= env->maxtl) {
> - cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
> + cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
> " Error state", cs->exception_index, env->tl, env->maxtl);
> return;
> }
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index eece271..f91ed93 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -236,26 +236,22 @@ void helper_cp1_putc(target_ulong x)
> #ifdef CONFIG_USER_ONLY
> void switch_mode(CPUUniCore32State *env, int mode)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (mode != ASR_MODE_USER) {
> - cpu_abort(env, "Tried to switch out of user mode\n");
> + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
> }
> }
>
> void uc32_cpu_do_interrupt(CPUState *cs)
> {
> - UniCore32CPU *cpu = UNICORE32_CPU(cs);
> - CPUUniCore32State *env = &cpu->env;
> -
> - cpu_abort(env, "NO interrupt in user mode\n");
> + cpu_abort(cs, "NO interrupt in user mode\n");
> }
>
> int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int access_type, int mmu_idx)
> {
> - UniCore32CPU *cpu = UNICORE32_CPU(cs);
> - CPUUniCore32State *env = &cpu->env;
> -
> - cpu_abort(env, "NO mmu fault in user mode\n");
> + cpu_abort(cs, "NO mmu fault in user mode\n");
> return 1;
> }
> #endif
> diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
> index d0527e5..8c2acf2 100644
> --- a/target-unicore32/softmmu.c
> +++ b/target-unicore32/softmmu.c
> @@ -33,6 +33,8 @@
> /* Map CPU modes onto saved register banks. */
> static inline int bank_number(CPUUniCore32State *env, int mode)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> switch (mode) {
> case ASR_MODE_USER:
> case ASR_MODE_SUSR:
> @@ -46,7 +48,7 @@ static inline int bank_number(CPUUniCore32State *env, int
> mode)
> case ASR_MODE_INTR:
> return 4;
> }
> - cpu_abort(env, "Bad mode %x\n", mode);
> + cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
> return -1;
> }
>
> @@ -99,7 +101,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
> addr = 0x18;
> break;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> return;
> }
> /* High vectors. */
> @@ -121,6 +123,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env,
> uint32_t address,
> int access_type, int is_user, uint32_t *phys_ptr, int *prot,
> target_ulong *page_size)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int code;
> uint32_t table;
> uint32_t desc;
> @@ -167,11 +170,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env,
> uint32_t address,
> *page_size = TARGET_PAGE_SIZE;
> break;
> default:
> - cpu_abort(env, "wrong page type!");
> + cpu_abort(CPU(cpu), "wrong page type!");
> }
> break;
> default:
> - cpu_abort(env, "wrong page type!");
> + cpu_abort(CPU(cpu), "wrong page type!");
> }
>
> *phys_ptr = phys_addr;
> @@ -267,6 +270,6 @@ hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr
> addr)
> {
> UniCore32CPU *cpu = UNICORE32_CPU(cs);
>
> - cpu_abort(&cpu->env, "%s not supported yet\n", __func__);
> + cpu_abort(CPU(cpu), "%s not supported yet\n", __func__);
> return addr;
> }
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index b4bee99..532d825 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -179,7 +179,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> #define UCOP_SET_L UCOP_SET(24)
> #define UCOP_SET_S UCOP_SET(24)
>
> -#define ILLEGAL cpu_abort(env, \
> +#define ILLEGAL cpu_abort(CPU(cpu), \
> "Illegal UniCore32 instruction %x at line %d!", \
> insn, __LINE__)
>
> @@ -187,6 +187,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp, tmp2, tmp3;
> if ((insn & 0xfe000000) == 0xe0000000) {
> tmp2 = new_tmp();
> @@ -212,6 +213,7 @@ static void disas_cp0_insn(CPUUniCore32State *env,
> DisasContext *s,
> static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
>
> if ((insn & 0xff003fff) == 0xe1000400) {
> @@ -692,6 +694,7 @@ static inline long ucf64_reg_offset(int reg)
> /* UniCore-F64 single load/store I_offset */
> static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int offset;
> TCGv tmp;
> TCGv addr;
> @@ -738,6 +741,7 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env,
> DisasContext *s, uint32_t in
> /* UniCore-F64 load/store multiple words */
> static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int i;
> int j, n, freg;
> TCGv tmp;
> @@ -823,6 +827,7 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env,
> DisasContext *s, uint32_t in
> /* UniCore-F64 mrc/mcr */
> static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t
> insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
>
> if ((insn & 0xfe0003ff) == 0xe2000000) {
> @@ -887,6 +892,8 @@ static void do_ucf64_trans(CPUUniCore32State *env,
> DisasContext *s, uint32_t ins
> /* UniCore-F64 convert instructions */
> static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t
> insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (UCOP_UCF64_FMT == 3) {
> ILLEGAL;
> }
> @@ -953,6 +960,8 @@ static void do_ucf64_fcvt(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn
> /* UniCore-F64 compare instructions */
> static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t
> insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (UCOP_SET(25)) {
> ILLEGAL;
> }
> @@ -1031,6 +1040,8 @@ static void do_ucf64_fcmp(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn
> /* UniCore-F64 data processing */
> static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t
> insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (UCOP_UCF64_FMT == 3) {
> ILLEGAL;
> }
> @@ -1064,6 +1075,8 @@ static void do_ucf64_datap(CPUUniCore32State *env,
> DisasContext *s, uint32_t ins
> /* Disassemble an F64 instruction */
> static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (!UCOP_SET(29)) {
> if (UCOP_SET(26)) {
> do_ucf64_ldst_m(env, s, insn);
> @@ -1170,6 +1183,8 @@ static void gen_exception_return(DisasContext *s, TCGv
> pc)
> static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> switch (UCOP_CPNUM) {
> #ifndef CONFIG_USER_ONLY
> case 0:
> @@ -1184,13 +1199,14 @@ static void disas_coproc_insn(CPUUniCore32State *env,
> DisasContext *s,
> break;
> default:
> /* Unknown coprocessor. */
> - cpu_abort(env, "Unknown coprocessor!");
> + cpu_abort(CPU(cpu), "Unknown coprocessor!");
> }
> }
>
> /* data processing instructions */
> static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
> TCGv tmp2;
> int logic_cc;
> @@ -1424,6 +1440,7 @@ static void do_mult(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn)
> /* miscellaneous instructions */
> static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val;
> TCGv tmp;
>
> @@ -1549,6 +1566,7 @@ static void do_ldst_ir(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn)
> /* SWP instruction */
> static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv addr;
> TCGv tmp;
> TCGv tmp2;
> @@ -1576,6 +1594,7 @@ static void do_swap(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn)
> /* load/store hw/sb */
> static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t
> insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv addr;
> TCGv tmp;
>
> @@ -1628,6 +1647,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn)
> /* load/store multiple words */
> static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val, i, mmu_idx;
> int j, n, reg, user, loaded_base;
> TCGv tmp;
> @@ -1769,6 +1789,7 @@ static void do_ldst_m(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn)
> /* branch (and link) */
> static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val;
> int32_t offset;
> TCGv tmp;
> @@ -1798,6 +1819,7 @@ static void do_branch(CPUUniCore32State *env,
> DisasContext *s, uint32_t insn)
>
> static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int insn;
>
> if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> @@ -1981,7 +2003,7 @@ static inline void
> gen_intermediate_code_internal(UniCore32CPU *cpu,
> if (dc->condjmp) {
> /* FIXME: This can theoretically happen with self-modifying
> code. */
> - cpu_abort(env, "IO on conditional branch instruction");
> + cpu_abort(cs, "IO on conditional branch instruction");
> }
> gen_io_end();
> }
> diff --git a/target-unicore32/ucf64_helper.c b/target-unicore32/ucf64_helper.c
> index a516edd..34fa2a5 100644
> --- a/target-unicore32/ucf64_helper.c
> +++ b/target-unicore32/ucf64_helper.c
> @@ -76,6 +76,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
>
> void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int i;
> uint32_t changed;
>
> @@ -99,7 +100,7 @@ void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env,
> uint32_t val)
> i = float_round_down;
> break;
> default: /* 100 and 101 not implement */
> - cpu_abort(env, "Unsupported UniCore-F64 round mode");
> + cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode");
> }
> set_float_rounding_mode(i, &env->ucf64.fp_status);
> }
> diff --git a/translate-all.c b/translate-all.c
> index 37b573b..356f2ca 100644
> --- a/translate-all.c
> +++ b/translate-all.c
> @@ -682,7 +682,7 @@ static void page_flush_tb(void)
> /* XXX: tb_flush is currently not thread safe */
> void tb_flush(CPUArchState *env1)
> {
> - CPUState *cpu;
> + CPUState *cpu = ENV_GET_CPU(env1);
>
> #if defined(DEBUG_FLUSH)
> printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
> @@ -693,7 +693,7 @@ void tb_flush(CPUArchState *env1)
> #endif
> if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)
> > tcg_ctx.code_gen_buffer_size) {
> - cpu_abort(env1, "Internal error: code buffer overflow\n");
> + cpu_abort(cpu, "Internal error: code buffer overflow\n");
> }
> tcg_ctx.tb_ctx.nb_tbs = 0;
>
> @@ -1379,12 +1379,11 @@ void tb_invalidate_phys_addr(hwaddr addr)
>
> void tb_check_watchpoint(CPUState *cpu)
> {
> - CPUArchState *env = cpu->env_ptr;
> TranslationBlock *tb;
>
> tb = tb_find_pc(cpu->mem_io_pc);
> if (!tb) {
> - cpu_abort(env, "check_watchpoint: could not find TB for pc=%p",
> + cpu_abort(cpu, "check_watchpoint: could not find TB for pc=%p",
> (void *)cpu->mem_io_pc);
> }
> cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc);
> @@ -1395,7 +1394,6 @@ void tb_check_watchpoint(CPUState *cpu)
> /* mask must never be zero, except for A20 change call */
> static void tcg_handle_interrupt(CPUState *cpu, int mask)
> {
> - CPUArchState *env = cpu->env_ptr;
> int old_mask;
>
> old_mask = cpu->interrupt_request;
> @@ -1414,7 +1412,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int
> mask)
> cpu->icount_decr.u16.high = 0xffff;
> if (!cpu_can_do_io(cpu)
> && (mask & ~old_mask) != 0) {
> - cpu_abort(env, "Raised interrupt while not in I/O function");
> + cpu_abort(cpu, "Raised interrupt while not in I/O function");
> }
> } else {
> cpu->tcg_exit_req = 1;
> @@ -1427,7 +1425,9 @@ CPUInterruptHandler cpu_interrupt_handler =
> tcg_handle_interrupt;
> must be at the end of the TB */
> void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> {
> +#if defined(TARGET_MIPS) || defined(TARGET_SH4)
> CPUArchState *env = cpu->env_ptr;
> +#endif
> TranslationBlock *tb;
> uint32_t n, cflags;
> target_ulong pc, cs_base;
> @@ -1435,7 +1435,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
>
> tb = tb_find_pc(retaddr);
> if (!tb) {
> - cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
> + cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
> (void *)retaddr);
> }
> n = cpu->icount_decr.u16.low + tb->icount;
> @@ -1465,7 +1465,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> #endif
> /* This should never happen. */
> if (n > CF_COUNT_MASK) {
> - cpu_abort(env, "TB too big during recompile");
> + cpu_abort(cpu, "TB too big during recompile");
> }
>
> cflags = n | CF_LAST_IO;
target-openrisc: Tested-by: Jia Liu <address@hidden>
> --
> 1.8.1.4
>
- [Qemu-devel] [RFC qom-cpu 31/41] exec: Change memory_region_section_get_iotlb() argument to CPUState, (continued)
- [Qemu-devel] [RFC qom-cpu 31/41] exec: Change memory_region_section_get_iotlb() argument to CPUState, Andreas Färber, 2013/09/04
- [Qemu-devel] [RFC qom-cpu 32/41] cputlb: Change tlb_set_page() argument to CPUState, Andreas Färber, 2013/09/04
- [Qemu-devel] [RFC qom-cpu 38/41] target-lm32: Move features field from CPULM32State to LM32CPU, Andreas Färber, 2013/09/04
- [Qemu-devel] [RFC qom-cpu 41/41] user-exec: Change exception_action() argument to CPUState, Andreas Färber, 2013/09/04
- [Qemu-devel] [RFC qom-cpu 37/41] target-microblaze: Replace DisasContext::env field with MicroBlazeCPU, Andreas Färber, 2013/09/04
- [Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() argument to CPUState, Andreas Färber, 2013/09/04
- [Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState, Andreas Färber, 2013/09/04
- [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() argument to CPUState, Andreas Färber, 2013/09/04
- Re: [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() argument to CPUState,
Jia Liu <=
- Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, pa rt 13: Emptying CPU_COMMON, Michael Walle, 2013/09/09
- Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON, Peter Maydell, 2013/09/09
- Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON, Michael Walle, 2013/09/17
- Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON, Richard Henderson, 2013/09/17
- Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON, Peter Maydell, 2013/09/17
- [Qemu-devel] Stopping the VM due to an illegal instruct ion [was: QOM CPUState, part 13: Emptying CPU_COMMON ], Michael Walle, 2013/09/20
Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON, Michael Walle, 2013/09/17