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Re: [Qemu-devel] [RFC] TCI for ARM and other hosts with aligned args


From: Stefan Weil
Subject: Re: [Qemu-devel] [RFC] TCI for ARM and other hosts with aligned args
Date: Wed, 11 Sep 2013 00:04:31 +0200
User-agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130803 Thunderbird/17.0.8

Am 10.09.2013 23:52, schrieb Richard Henderson:
> On 09/10/2013 02:34 PM, Stefan Weil wrote:
>> For native compilations, TCG_TARGET_CALL_ALIGN_ARGS can be set from
>> configure.  Cross compilations cannot set that macro automatically
>> (or is there some way to do this?)
> I can't think of a way that would be reasonable from configure.
>
>> Should we use this mechanism for all hosts (and move the definitions in
>> tcg-target.h to a conditional definition in tcg.h), or should we use it only 
>> for TCI?
> I'd prefer a common solution, but it's something easy to get wrong
> if there are multiple ABIs in play, e.g. PPC32.
>
> Perhaps let's start with just TCI.
>
>> The alpha disassembler does not work on 32 bit hosts,
>> therefore debugging is difficult.
> It works on i386.  What's your "not working" test case?
>
>
> r~

busybox-static from Debian running on 32 bit Linux:

$ alpha-linux-user/qemu-alpha -d in_asm
/usr/gnemul/qemu-alpha/bin/busybox pwd
host mmap_min_addr=0x10000
Reserved 0x21e000 bytes of guest address space
Relocating guest address space from 0x0000000020000000 to 0x20000000
guest_base  0x0
start    end      size     prot
0000000020000000-0000000020218000 0000000000218000 rwx
0000000040000000-0000000040002000 0000000000002000 ---
0000000040002000-0000000040802000 0000000000800000 rw-
0000000020216000-000000012021e000 0000000100008000 rwx
start_brk   0x0000000000000000
end_code    0x00000001202179bd
start_code  0x0000000120000000
start_data  0x0000000120000000
end_data    0x00000001202179bd
start_stack 0x0000000040801160
brk         0x000000012021dcb0
entry       0x00000001200d3fe0
IN:
0x00000001200d3fe0:  stq_c    zero,23096(t12)
0x00000001200d3fe4:  stq_c    zero,23096(t12)
0x00000001200d3fe8:  stq_c    zero,23096(t12)
0x00000001200d3fec:  stq_c    zero,23096(t12)
0x00000001200d3ff0:  stq_c    zero,23096(t12)
0x00000001200d3ff4:  stq_c    zero,23096(t12)
0x00000001200d3ff8:  stq_c    zero,23096(t12)
0x00000001200d3ffc:  stq_c    zero,23096(t12)




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