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[Qemu-devel] [PATCH v4 27/33] tcg-aarch64: Pass return address to load/s
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 27/33] tcg-aarch64: Pass return address to load/store helpers directly. |
Date: |
Sat, 14 Sep 2013 14:54:44 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
include/exec/exec-all.h | 11 -----------
tcg/aarch64/tcg-target.c | 44 ++++++++++++++++++++++++++------------------
2 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index beb4149..8b106f5 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -340,17 +340,6 @@ static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
ra += b; /* apply the displacement */
return ra;
}
-# elif defined(__aarch64__)
-# define GETRA_LDST(RA) tcg_getra_ldst(RA)
-static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
-{
- int32_t b;
- ra += 4; /* skip one instruction */
- b = *(int32_t *)ra; /* load the branch insn */
- b = (b << 6) >> (6 - 2); /* extract the displacement */
- ra += b; /* apply the displacement */
- return ra;
-}
# endif
#endif /* CONFIG_QEMU_LDST_OPTIMIZATION */
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 1905271..ce3c17b 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1038,39 +1038,46 @@ static inline void tcg_out_addsub2(TCGContext *s, int
ext, TCGReg rl,
}
}
-static inline void tcg_out_nop(TCGContext *s)
-{
- tcg_out32(s, 0xd503201f);
-}
-
#ifdef CONFIG_SOFTMMU
-/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
- int mmu_idx) */
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ * int mmu_idx, uintptr_t ra)
+ */
static const void * const qemu_ld_helpers[4] = {
- helper_ldb_mmu,
- helper_ldw_mmu,
- helper_ldl_mmu,
- helper_ldq_mmu,
+ helper_ret_ldub_mmu,
+ helper_ret_lduw_mmu,
+ helper_ret_ldul_mmu,
+ helper_ret_ldq_mmu,
};
-/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
- uintxx_t val, int mmu_idx) */
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, int mmu_idx, uintptr_t ra)
+ */
static const void * const qemu_st_helpers[4] = {
- helper_stb_mmu,
- helper_stw_mmu,
- helper_stl_mmu,
- helper_stq_mmu,
+ helper_ret_stb_mmu,
+ helper_ret_stw_mmu,
+ helper_ret_stl_mmu,
+ helper_ret_stq_mmu,
};
+static inline void tcg_out_adr(TCGContext *s, TCGReg rd, tcg_target_long addr)
+{
+ addr -= (tcg_target_long)s->code_ptr;
+ assert(addr == sextract64(addr, 0, 21));
+ tcg_fmt_Rd_disp21(s, INSN_ADR, rd, addr);
+}
+
static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
+ tcg_out_adr(s, TCG_REG_X3, (uintptr_t)lb->raddr);
+
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
(tcg_target_long)qemu_ld_helpers[lb->opc & 3]);
tcg_out_callr(s, TCG_REG_TMP);
+
if (lb->opc & 0x04) {
tcg_out_sxt(s, 1, lb->opc & 3, lb->datalo_reg, TCG_REG_X0);
} else {
@@ -1088,11 +1095,12 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
+ tcg_out_adr(s, TCG_REG_X4, (uintptr_t)lb->raddr);
+
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
(tcg_target_long)qemu_st_helpers[lb->opc & 3]);
tcg_out_callr(s, TCG_REG_TMP);
- tcg_out_nop(s);
tcg_out_goto(s, (tcg_target_long)lb->raddr);
}
--
1.8.3.1
- [Qemu-devel] [PATCH v4 18/33] tcg-aarch64: Support add2, sub2, (continued)
- [Qemu-devel] [PATCH v4 18/33] tcg-aarch64: Support add2, sub2, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 19/33] tcg-aarch64: Support muluh, mulsh, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 20/33] tcg-aarch64: Support div, rem, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 21/33] tcg-aarch64: Introduce tcg_fmt_Rd_uimm, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 22/33] tcg-aarch64: Use MOVN in tcg_out_movi, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 23/33] tcg-aarch64: Use ORRI in tcg_out_movi, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 24/33] tcg-aarch64: Special case small constants in tcg_out_movi, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 25/33] tcg-aarch64: Use adrp in tcg_out_movi, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 26/33] tcg-aarch64: Avoid add with zero in tlb load, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 27/33] tcg-aarch64: Pass return address to load/store helpers directly.,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 28/33] tcg-aarch64: Use tcg_out_call for qemu_ld/st, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 30/33] tcg-aarch64: Implement tcg_register_jit, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 29/33] tcg-aarch64: Use symbolic names for branches, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 31/33] tcg-aarch64: Reuse FP and LR in translated code, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 32/33] tcg-aarch64: Introduce tcg_out_ldst_pair, Richard Henderson, 2013/09/14
- [Qemu-devel] [PATCH v4 33/33] tcg-aarch64: Remove redundant CPU_TLB_ENTRY_BITS check, Richard Henderson, 2013/09/14