Re: [Qemu-devel] [PATCH v4 3/3] hw/pci: handle downstream pci master abort

[Peter Maydell]

On 16 September 2013 07:14, Michael S. Tsirkin <address@hidden> wrote:
> On Sun, Sep 15, 2013 at 10:41:26PM +0100, Peter Maydell wrote:
>> On 15 September 2013 22:07, Michael S. Tsirkin <address@hidden> wrote:
>> > On Sun, Sep 15, 2013 at 09:40:37PM +0100, Peter Maydell wrote:
>> >> "native" means "if the device's MMIO callback does 'return 0x12345678;'
>> >> for a 32 bit read then the guest CPU should see 0x12345678". That's
>> >> almost always what you want for simple devices (which may in fact
>> >> only support 32 bit accesses to registers), because it means you don't
>> >> have to fill your device with explicit endianness swaps.
>> >
>> > But this means that you device behaves differently
>> > depending on the endian-ness of the guest system.
>> > So it only makes sense if the device is very
>> > system specific
>>
>> If you mark a device as specifically DEVICE_LITTLE_ENDIAN
>> or DEVICE_BIG_ENDIAN this is *also* very system specific.
>
> No, this just means the device is always wired in
> the same way on all systems. It's the pragmatic
> choice for any bus that supports device plug-in.

No, it means the device is little endian even on a big
endian system. On BE systems that is weird, and the only
reason for it is if it's an external bus with a standard that
specifies which endianness it is. That's true for ISA and PCI
(and this is where we're using the device's endianness
specification to compensate for the fact we don't have a way
to specify that PCI host bridges will do endianness swapping
on a bigendian system).
But "pluggable bus" is not equivalent to "system specific"
(in either direction).

-- PMM