[Qemu-devel] [PATCH 25/60] AArch64: Add SIMD shl instruction emulation

[Alexander Graf]

This patch adds emulation support for the SIMD shl instruction. It belongs
to the same instruction group as ushll and can probably be handled in a shared
function with that one eventually.

Signed-off-by: Alexander Graf <address@hidden>
---
 target-arm/translate-a64.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 6a3b34e..bc91324 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1225,6 +1225,53 @@ static void handle_ushll(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_tmp);
 }
 
+/* SIMD shift shl */
+static void handle_simdshl(DisasContext *s, uint32_t insn)
+{
+    int rd = get_bits(insn, 0, 5);
+    int rn = get_bits(insn, 5, 5);
+    int immh = get_bits(insn, 19, 4);
+    bool is_q = get_bits(insn, 30, 1);
+    int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]);
+    int freg_offs_n = offsetof(CPUARMState, vfp.regs[rn * 2]);
+    TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+    int i;
+    int ebytes;
+    int size;
+    int shift = get_bits(insn, 16, 7);
+
+    size = clz32(immh) - (31 - 4);
+
+    if (size > 3) {
+        /* XXX implement 128bit operations */
+        unallocated_encoding(s);
+        return;
+    }
+
+    ebytes = 1 << size;
+    shift -= (8 << size);
+
+    if (!immh) {
+        /* XXX see asimdimm */
+        unallocated_encoding(s);
+        return;
+    }
+
+    for (i = 0; i < (16 / ebytes); i++) {
+        simd_ld(tcg_tmp, freg_offs_n + (i * ebytes), size);
+        tcg_gen_shli_i64(tcg_tmp, tcg_tmp, shift);
+        simd_st(tcg_tmp, freg_offs_d + (i * ebytes), size);
+    }
+
+    if (!is_q) {
+        TCGv_i64 tcg_zero = tcg_const_i64(0);
+        simd_st(tcg_zero, freg_offs_d + sizeof(float64), 3);
+        tcg_temp_free_i64(tcg_zero);
+    }
+
+    tcg_temp_free_i64(tcg_tmp);
+}
+
 void disas_a64_insn(CPUARMState *env, DisasContext *s)
 {
     uint32_t insn;
@@ -1311,6 +1358,9 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
         } else if (!get_bits(insn, 31, 1) && !get_bits(insn, 23, 1) &&
                    (get_bits(insn, 10, 6) == 0x29)) {
             handle_ushll(s, insn);
+        } else if (!get_bits(insn, 31, 1) && !get_bits(insn, 23, 1) &&
+                   (get_bits(insn, 10, 6) == 0x15)) {
+            handle_simdshl(s, insn);
         } else {
             unallocated_encoding(s);
         }
-- 
1.7.12.4