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[Qemu-devel] [PATCH 51/60] AArch64: Add fmov (scalar, immediate) instruc
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 51/60] AArch64: Add fmov (scalar, immediate) instruction |
Date: |
Fri, 27 Sep 2013 02:48:45 +0200 |
This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alexander Graf <address@hidden>
---
target-arm/translate-a64.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 654e011..33163fd 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1884,6 +1884,39 @@ static void handle_fpfpconv(DisasContext *s, uint32_t
insn)
handle_fpfpcvt(s, insn, direction, ROUND_MODE_ZERO);
}
+/* fmov (immediate) */
+static void handle_fmovi(DisasContext *s, uint32_t insn)
+{
+ int rd = get_reg(insn);
+ int imm8 = get_bits(insn, 13, 8);
+ int is_double = get_bits(insn, 22, 2);
+ uint64_t imm;
+ int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]);
+ TCGv_i64 tcg_res;
+
+ if (is_double > 1) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (is_double) {
+ imm = (get_bits(imm8, 7, 1) ? 0x8000 : 0) |
+ (get_bits(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
+ get_bits(imm8, 0, 6);
+ imm <<= 48;
+ } else {
+ imm = (get_bits(imm8, 7, 1) ? 0x8000 : 0) |
+ (get_bits(imm8, 6, 1) ? 0x3e00 : 0x4000) |
+ (get_bits(imm8, 0, 6) << 3);
+ imm <<= 16;
+ }
+
+ tcg_res = tcg_const_i64(imm);
+ clear_fpreg(rd);
+ tcg_gen_st_i64(tcg_res, cpu_env, freg_offs_d);
+ tcg_temp_free_i64(tcg_res);
+}
+
/* SIMD ORR */
static void handle_simdorr(DisasContext *s, uint32_t insn)
{
@@ -2466,6 +2499,9 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
case 0x1e:
if (!get_bits(insn, 21, 1) && !get_bits(insn, 30, 1)) {
handle_fpfpconv(s, insn);
+ } else if (!get_bits(insn, 29, 3) && get_bits(insn, 21, 1) &&
+ (get_bits(insn, 5, 8) == 0x80)) {
+ handle_fmovi(s, insn);
} else {
unallocated_encoding(s);
}
--
1.7.12.4
- [Qemu-devel] [PATCH 47/60] AArch64: Add clz instruction emulation, (continued)
- [Qemu-devel] [PATCH 47/60] AArch64: Add clz instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 40/60] AArch64: Add tbz instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 46/60] AArch64: Add rev instruction family emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 48/60] AArch64: Add 0x1a encoding of add instructions, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 44/60] AArch64: Add division instruction family emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 41/60] AArch64: Add ldr/str instruction family emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 49/60] AArch64: Add "Data-processing (3 source)" instruction, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 51/60] AArch64: Add fmov (scalar, immediate) instruction,
Alexander Graf <=
- [Qemu-devel] [PATCH 56/60] AArch64: Add "Floating-point data-processing (2, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 58/60] AArch64: Add "ADD (vector)" instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 57/60] AArch64: Add "Floating-point data-processing (2, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 42/60] AArch64: Add literal ld instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 50/60] AArch64: Add "Floating-point<->fixed-point, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 52/60] AArch64: Add "Floating-point<->integer conversions", Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 59/60] AArch64: Add "Floating-point data-processing (3, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 53/60] AArch64: Add "Floating-point compare" instruction, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 54/60] AArch64: Add "Floating-point data-processing (1, Alexander Graf, 2013/09/26