[Qemu-devel] Update the id of Vexpress Cortex-A9 from r0p0 to r0p1?

[Mian Yousaf Kaukab]

Hi,

Default vexpress_defconfig does not boot on qemu vexpress-a9 target. In kernel,
vexpress uart detection for DEBUG_LL is done using Coretex-A9 id. Only r0p1 is
mapped to legacy map. All other variants are mapped to RS1/aseries map.

As qemu vexpress-a9 target reports Cortex-A9 version as r0p0, kernel maps uart0
at address 0x1c090000 instead of 0x10009000. This result in kernel indefinitely
waiting for uart during boot. A kernel patch to fix this was discussed
in the following link
http://comments.gmane.org/gmane.linux.ports.arm.kernel/269657 .
In this discussion Pawel Moll mentioned that V2P-CA9 has Cortex-A9 r0p1 and not
r0p0. If this is correct, to fix this and similar future problems, shouldn't
qemu Cortex-A9 be updated to version r0p1?

So what will it take to update the id of Cortex-A9 in qemu from r0p0 to r0p1?

I started looking at differences between r0p0 and r0p1, which can be found at
the following link
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CACDGEDG.html

The increase in micro TLB entries should not make a difference as qemu is not
cycle accurate and with a quick search in ARM documentation I couldn't find
any register showing number of micro TLB entries. Note that the change is in
micro TLB and not in unified TLB.

However, I am not sure if the engineering errata implemented in r0p1 will
require any change in qemu. Anyone have more information about this?

Any other IPs that will need to be updated along with the ARM core?

Sincerely,

Yousaf