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[Qemu-devel] [PATCH 15/19] Add VSX xmax/xmin Instructions
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From: |
Tom Musta |
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Subject: |
[Qemu-devel] [PATCH 15/19] Add VSX xmax/xmin Instructions |
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Date: |
Thu, 24 Oct 2013 11:26:12 -0500 |
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User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 |
This patch adds the VSX floating point maximum and minimum
instructions:
- xsmaxdp, xvmaxdp, xvmaxsp
- xsmindp, xvmindp, xvminsp
Because of the Power ISA definitions of maximum and minimum
on various boundary cases, the standard softfloat comparison
routines (e.g. float64_lt) do not work as well as one might
think. Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/fpu_helper.c | 162 +++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/helper.h | 6 ++
target-ppc/translate.c | 12 ++++
3 files changed, 180 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 0373913..29b27ce 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2323,3 +2323,165 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_SCALAR_CMP(xscmpodp, 1)
VSX_SCALAR_CMP(xscmpudp, 0)
+
+#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ul)
+
+static int compare_float64(float64 a, float64 b)
+{
+ uint64_t asgn = a & 0x8000000000000000ul;
+ uint64_t bsgn = b & 0x8000000000000000ul;
+
+ if (asgn != bsgn) {
+ return asgn ? -1 : 1;
+ }
+
+ uint64_t aexp = (a & 0x7FF0000000000000ul) >> (64-12);
+ uint64_t bexp = (b & 0x7FF0000000000000ul) >> (64-12);
+
+ if (aexp < bexp) {
+ return asgn ? 1 : -1;
+ } else if (aexp > bexp) {
+ return asgn ? -1 : 1;
+ } else {
+ uint64_t afrac = a & 0x000FFFFFFFFFFFFFul;
+ uint64_t bfrac = b & 0x000FFFFFFFFFFFFFul;
+
+ if (afrac < bfrac) {
+ return asgn ? 1 : -1;
+ } else if (afrac > bfrac) {
+ return asgn ? -1 : 1;
+ } else {
+ return 0;
+ }
+ }
+}
+
+#define float32_snan_to_qnan(x) ((x) | 0x00400000)
+
+static int compare_float32(float32 a, float32 b)
+{
+ uint64_t asgn = a & 0x80000000;
+ uint64_t bsgn = b & 0x80000000;
+
+ if (asgn != bsgn) {
+ return asgn ? -1 : 1;
+ }
+
+ uint64_t aexp = (a & 0x7FC00000) >> (32-9);
+ uint64_t bexp = (b & 0x7FF00000) >> (32-9);
+
+ if (aexp < bexp) {
+ return asgn ? 1 : -1;
+ } else if (aexp > bexp) {
+ return asgn ? -1 : 1;
+ } else {
+ uint64_t afrac = a & 0x007FFFFF;
+ uint64_t bfrac = b & 0x007FFFFF;
+
+ if (afrac < bfrac) {
+ return asgn ? 1 : -1;
+ } else if (afrac > bfrac) {
+ return asgn ? -1 : 1;
+ } else {
+ return 0;
+ }
+ }
+}
+
+/* VSX_MAX - VSX floating point maximum
+ * op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp - type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ */
+#define VSX_MAX(op, nels, tp, fld) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ int i; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xB(opcode), &xb, env); \
+ getVSR(xT(opcode), &xt, env); \
+ \
+ for (i = 0; i < nels; i++) { \
+ if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
+ tp##_is_any_nan(xb.fld[i]))) { \
+ if (tp##_is_signaling_nan(xa.fld[i])) { \
+ xt.fld[i] = tp##_snan_to_qnan(xa.fld[i]); \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } else if (tp##_is_signaling_nan(xb.fld[i])) { \
+ xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]); \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } else if (tp##_is_quiet_nan(xb.fld[i])) { \
+ xt.fld[i] = xa.fld[i]; \
+ } else { /* XA is QNaN */ \
+ xt.fld[i] = xb.fld[i]; \
+ } \
+ } else if (unlikely(tp##_is_infinity(xa.fld[i]))) { \
+ xt.fld[i] = tp##_is_neg(xa.fld[i]) ? xb.fld[i] : xa.fld[i]; \
+ } else if (unlikely(tp##_is_infinity(xb.fld[i]))) { \
+ xt.fld[i] = tp##_is_neg(xb.fld[i]) ? xa.fld[i] : xb.fld[i]; \
+ } \
+ else { \
+ xt.fld[i] = (compare_##tp(xa.fld[i], xb.fld[i]) < 0) ? \
+ xb.fld[i] : xa.fld[i]; \
+ } \
+ } \
+ \
+ putVSR(xT(opcode), &xt, env); \
+ helper_float_check_status(env); \
+}
+
+VSX_MAX(xsmaxdp, 1, float64, f64)
+VSX_MAX(xvmaxdp, 2, float64, f64)
+VSX_MAX(xvmaxsp, 4, float32, f32)
+
+/* VSX_MIN - VSX floating point minimum
+ * op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp - type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ */
+#define VSX_MIN(op, nels, tp, fld) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ int i; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xB(opcode), &xb, env); \
+ getVSR(xT(opcode), &xt, env); \
+ \
+ for (i = 0; i < nels; i++) { \
+ if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
+ tp##_is_any_nan(xb.fld[i]))) { \
+ if (tp##_is_signaling_nan(xa.fld[i])) { \
+ xt.fld[i] = tp##_snan_to_qnan(xa.fld[i]); \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } else if (tp##_is_signaling_nan(xb.fld[i])) { \
+ xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]); \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } else if (tp##_is_quiet_nan(xb.fld[i])) { \
+ xt.fld[i] = xa.fld[i]; \
+ } else { /* XA is QNaN */ \
+ xt.fld[i] = xb.fld[i]; \
+ } \
+ } else if (unlikely(tp##_is_infinity(xa.fld[i]))) { \
+ xt.fld[i] = tp##_is_neg(xa.fld[i]) ? xa.fld[i] : xb.fld[i]; \
+ } else if (unlikely(tp##_is_infinity(xb.fld[i]))) { \
+ xt.fld[i] = tp##_is_neg(xb.fld[i]) ? xb.fld[i] : xa.fld[i]; \
+ } \
+ else { \
+ xt.fld[i] = (compare_##tp(xa.fld[i], xb.fld[i]) < 0) ? \
+ xa.fld[i] : xb.fld[i]; \
+ } \
+ } \
+ \
+ putVSR(xT(opcode), &xt, env); \
+ helper_float_check_status(env); \
+}
+
+VSX_MIN(xsmindp, 1, float64, f64)
+VSX_MIN(xvmindp, 2, float64, f64)
+VSX_MIN(xvminsp, 4, float32, f32)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index bfb1964..40c523a 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -270,6 +270,8 @@ DEF_HELPER_2(xsnmsubadp, void, env, i32)
DEF_HELPER_2(xsnmsubmdp, void, env, i32)
DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
+DEF_HELPER_2(xsmaxdp, void, env, i32)
+DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -288,6 +290,8 @@ DEF_HELPER_2(xvnmaddadp, void, env, i32)
DEF_HELPER_2(xvnmaddmdp, void, env, i32)
DEF_HELPER_2(xvnmsubadp, void, env, i32)
DEF_HELPER_2(xvnmsubmdp, void, env, i32)
+DEF_HELPER_2(xvmaxdp, void, env, i32)
+DEF_HELPER_2(xvmindp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -306,6 +310,8 @@ DEF_HELPER_2(xvnmaddasp, void, env, i32)
DEF_HELPER_2(xvnmaddmsp, void, env, i32)
DEF_HELPER_2(xvnmsubasp, void, env, i32)
DEF_HELPER_2(xvnmsubmsp, void, env, i32)
+DEF_HELPER_2(xvmaxsp, void, env, i32)
+DEF_HELPER_2(xvminsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 053df68..67d5267 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7312,6 +7312,8 @@ GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -7330,6 +7332,8 @@ GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
@@ -7348,6 +7352,8 @@ GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
#define VSX_LOGICAL(name, tcg_op) \
static void glue(gen_, name)(DisasContext * ctx) \
@@ -10050,6 +10056,8 @@ GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
+GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
+GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
@@ -10068,6 +10076,8 @@ GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
+GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
@@ -10086,6 +10096,8 @@ GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
+GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
#undef VSX_LOGICAL
#define VSX_LOGICAL(name, opc2, opc3, fl2) \
--
1.7.1
- Re: [Qemu-devel] [PATCH 10/19] Add VSX ISA2.06 xrsqrte Instructions, (continued)
- [Qemu-devel] [PATCH 11/19] Add VSX ISA2.06 xtdiv Instructions, Tom Musta, 2013/10/24
- [Qemu-devel] [PATCH 12/19] Add VSX ISA2.06 xtsqrt Instructions, Tom Musta, 2013/10/24
- [Qemu-devel] [PATCH 13/19] Add VSX ISA2.06 Multiply Add Instructions, Tom Musta, 2013/10/24
- [Qemu-devel] [PATCH 14/19] Add VSX xscmp*dp Instructions, Tom Musta, 2013/10/24
- [Qemu-devel] [PATCH 15/19] Add VSX xmax/xmin Instructions,
Tom Musta <=
- Re: [Qemu-devel] [PATCH 15/19] Add VSX xmax/xmin Instructions, Peter Maydell, 2013/10/24
[Qemu-devel] [PATCH 16/19] Add VSX Vector Compare Instructions, Tom Musta, 2013/10/24
[Qemu-devel] [PATCH 17/19] Add VSX Floating Point to Floating Point Conversion Instructions, Tom Musta, 2013/10/24
[Qemu-devel] [PATCH 18/19] Add VSX ISA2.06 Integer Conversion Instructions, Tom Musta, 2013/10/24