Re: [Qemu-devel] [PATCH 14/60] AArch64: Add orr instruction emulation

[Alexander Graf]

On 27.09.2013, at 11:25, Richard Henderson <address@hidden> wrote:

> On 09/26/2013 05:48 PM, Alexander Graf wrote:
>> This patch adds emulation support for the orr instruction.
>> 
>> Signed-off-by: Alexander Graf <address@hidden>
>> ---
>> target-arm/helper-a64.c    |  28 +++++++++++
>> target-arm/helper-a64.h    |   1 +
>> target-arm/translate-a64.c | 120 
>> +++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 149 insertions(+)
>> 
>> diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
>> index 8105fb5..da72b7f 100644
>> --- a/target-arm/helper-a64.c
>> +++ b/target-arm/helper-a64.c
>> @@ -24,3 +24,31 @@
>> #include "sysemu/sysemu.h"
>> #include "qemu/bitops.h"
>> 
>> +uint32_t HELPER(pstate_add)(uint32_t pstate, uint64_t a1, uint64_t a2,
>> +                            uint64_t ar)
>> +{
>> +    int64_t s1 = a1;
>> +    int64_t s2 = a2;
>> +    int64_t sr = ar;
>> +
>> +    pstate &= ~(PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V);
>> +
>> +    if (sr < 0) {
>> +        pstate |= PSTATE_N;
>> +    }
>> +
>> +    if (!ar) {
>> +        pstate |= PSTATE_Z;
>> +    }
>> +
>> +    if (ar && (ar < a1)) {
>> +        pstate |= PSTATE_C;
>> +    }
>> +
>> +    if ((s1 > 0 && s2 > 0 && sr < 0) ||
>> +        (s1 < 0 && s2 < 0 && sr > 0)) {
>> +        pstate |= PSTATE_V;
>> +    }
>> +
>> +    return pstate;
>> +}
> 
> Why are you not using the same split apart bits as A32?

There is an architecturally defined register that specifies what pstate looks 
like and IIRC that includes system level state as well, similar to EFLAGS. So I 
figured it's more straight forward to use a single variable for it.

I don't think it really makes much of a difference either way though. If we see 
that doing it in a split way makes more sense we can always just switch to that 
later.


Alex