Re: [Qemu-devel] [PATCH 14/60] AArch64: Add orr instruction emulation

[Peter Maydell]

On 31 October 2013 00:29, Alexander Graf <address@hidden> wrote:
>
> On 27.09.2013, at 11:25, Richard Henderson <address@hidden> wrote:
>> Why are you not using the same split apart bits as A32?
>
> There is an architecturally defined register that specifies
> what pstate looks like and IIRC that includes system level
> state as well, similar to EFLAGS.

No, the architecture goes out of its way to point out that pstate
is not a register. There are a collection of different state bits
which are generally accessible via different MSR/MRS
instructions or in some cases not accessible at all. This
is a difference from A32.

In any case as Richard says we already split NZCV from
the rest of CPSR in A32 -- the few places that want a
complete 32 bit CPSR call a helper function that assembles
it from the various separate parts.

> I don't think it really makes much of a difference either way
> though. If we see that doing it in a split way makes more
> sense we can always just switch to that later.

I think the split is less critical for A64 because of the
severely reduced conditionality which means we're less
likely to be making frequent NZCV checks. However it's
probably still worth having because it's pretty nearly free.

-- PMM