[Qemu-devel] [PATCH for-1.8 59/61] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v

[Richard Henderson]

And make the destination argument explicit.

Signed-off-by: Richard Henderson <address@hidden>
---
 target-i386/translate.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 61df97e..af8a27b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -384,9 +384,9 @@ static void gen_add_A0_im(DisasContext *s, int val)
     }
 }
 
-static inline void gen_op_jmp_T0(void)
+static inline void gen_op_jmp_v(TCGv dest)
 {
-    tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
+    tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip));
 }
 
 static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
@@ -423,7 +423,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int 
idx, int d)
 static inline void gen_jmp_im(target_ulong pc)
 {
     tcg_gen_movi_tl(cpu_tmp0, pc);
-    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
+    gen_op_jmp_v(cpu_tmp0);
 }
 
 /* Compute SEG:REG into A0.  SEG is selected from the override segment
@@ -4762,7 +4762,7 @@ static target_ulong disas_insn(CPUX86State *env, 
DisasContext *s,
             next_eip = s->pc - s->cs_base;
             tcg_gen_movi_tl(cpu_T[1], next_eip);
             gen_push_v(s, cpu_T[1]);
-            gen_op_jmp_T0();
+            gen_op_jmp_v(cpu_T[0]);
             gen_eob(s);
             break;
         case 3: /* lcall Ev */
@@ -4789,7 +4789,7 @@ static target_ulong disas_insn(CPUX86State *env, 
DisasContext *s,
             if (dflag == MO_16) {
                 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
             }
-            gen_op_jmp_T0();
+            gen_op_jmp_v(cpu_T[0]);
             gen_eob(s);
             break;
         case 5: /* ljmp Ev */
@@ -4806,7 +4806,7 @@ static target_ulong disas_insn(CPUX86State *env, 
DisasContext *s,
             } else {
                 gen_op_movl_seg_T0_vm(R_CS);
                 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
-                gen_op_jmp_T0();
+                gen_op_jmp_v(cpu_T[0]);
             }
             gen_eob(s);
             break;
@@ -6189,14 +6189,14 @@ static target_ulong disas_insn(CPUX86State *env, 
DisasContext *s,
         ot = gen_pop_T0(s);
         gen_stack_update(s, val + (1 << ot));
         /* Note that gen_pop_T0 uses a zero-extending load.  */
-        gen_op_jmp_T0();
+        gen_op_jmp_v(cpu_T[0]);
         gen_eob(s);
         break;
     case 0xc3: /* ret */
         ot = gen_pop_T0(s);
         gen_pop_update(s, ot);
         /* Note that gen_pop_T0 uses a zero-extending load.  */
-        gen_op_jmp_T0();
+        gen_op_jmp_v(cpu_T[0]);
         gen_eob(s);
         break;
     case 0xca: /* lret im */
@@ -6214,7 +6214,7 @@ static target_ulong disas_insn(CPUX86State *env, 
DisasContext *s,
             gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
             /* NOTE: keeping EIP updated is not a problem in case of
                exception */
-            gen_op_jmp_T0();
+            gen_op_jmp_v(cpu_T[0]);
             /* pop selector */
             gen_add_A0_im(s, 1 << dflag);
             gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
-- 
1.8.3.1