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[Qemu-devel] [PULL 4/7] target-openrisc: Correct wrong epcr register in
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PULL 4/7] target-openrisc: Correct wrong epcr register in interrupt handler |
Date: |
Wed, 20 Nov 2013 22:38:35 +0800 |
From: Sebastian Macke <address@hidden>
This patch corrects several misbehaviors during an interrupt process.
Most of the time the pc is already correct and therefore no special treatment
of the exceptions is necessary.
Tested by checking crashing programs which otherwise work in or1ksim.
Signed-off-by: Sebastian Macke <address@hidden>
Reviewed-by: Jia Liu <address@hidden>
Signed-off-by: Jia Liu <address@hidden>
---
target-openrisc/interrupt.c | 25 +++++++------------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 16ef4b3..2153e7e 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -30,26 +30,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
- if (env->flags & D_FLAG) { /* Delay Slot insn */
+
+ env->epcr = env->pc;
+ if (env->flags & D_FLAG) {
env->flags &= ~D_FLAG;
env->sr |= SR_DSX;
- if (env->exception_index == EXCP_TICK ||
- env->exception_index == EXCP_INT ||
- env->exception_index == EXCP_SYSCALL ||
- env->exception_index == EXCP_FPE) {
- env->epcr = env->jmp_pc;
- } else {
- env->epcr = env->pc - 4;
- }
- } else {
- if (env->exception_index == EXCP_TICK ||
- env->exception_index == EXCP_INT ||
- env->exception_index == EXCP_SYSCALL ||
- env->exception_index == EXCP_FPE) {
- env->epcr = env->npc;
- } else {
- env->epcr = env->pc;
- }
+ env->epcr -= 4;
+ }
+ if (env->exception_index == EXCP_SYSCALL) {
+ env->epcr += 4;
}
/* For machine-state changed between user-mode and supervisor mode,
--
1.8.3.4 (Apple Git-47)
- [Qemu-devel] [PULL 0/7] OpenRISC patch queue for 1.7, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 3/7] target-openrisc: Remove executable flag for every page, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 4/7] target-openrisc: Correct wrong epcr register in interrupt handler,
Jia Liu <=
- [Qemu-devel] [PULL 5/7] openrisc-timer: Reduce overhead, Separate clock update functions, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 6/7] target-openrisc: Correct memory bounds checking for the tlb buffers, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 7/7] target-openrisc: Correct carry flag check of l.addc and l.addic test cases, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 1/7] target-openrisc: Speed up move instruction, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 2/7] target-openrisc: Remove unnecessary code generated by jump instructions, Jia Liu, 2013/11/20