Re: [Qemu-devel] [PATCH arm-devs v1 2/6] target-arm/cpu: Convert reset CBAR to a property

[Peter Crosthwaite]

On Wed, Nov 27, 2013 at 9:47 PM, Peter Maydell <address@hidden> wrote:
> On 27 November 2013 11:39, Peter Crosthwaite
> <address@hidden> wrote:
>> Is the "periphbase" ever runtime configurable? If not I'm not sure we
>> need the "reset".
>
> You can't runtime configure it (it's a bunch of signals into the
> core that determine where the decoder sits the peripherals in
> the memory map).

So that is a top level signal of MPCore rather than A9 CPUs right?
Assuming so, that name "PERIPHBASE" is a ideally property of the the
mpcore container device. And in this ideal world that container
contains the A9 CPUs themselves and propagates "periphbase" through to
the CPU as "cbar" during its own init/realize. Looking at ARM docco,
the definition of CBAR == PERIPHBASE is A9MPCore specific. From ARM
infocentre:

----
Cortex-A9 Technical Reference ManualRevision: r4p1
Home > System Control > Register descriptions > Configuration Base
Address Register

4.3.24. Configuration Base Address Registe

...
Configurations

In Cortex-A9 uniprocessor implementations the base address is set to zero.

In Cortex-A9 MPCore implementations, the base address is reset to
PERIPHBASE[31:13] so that software can determine the location of the
private memory region"
---

So the best name for this register AFAICT is simply CBAR and either
MPCore container or whatever are responsible for setting it to an
appropriate value.

> However, the CBAR register which on reset
> starts out with the value of the base address is a writable
> register (writing it won't change where the peripherals live,
> it just reads-as-written).
>

So with that in mind i think the "reset-" prefix is appropriate.

Regards,
Peter

> -- PMM
>