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[Qemu-devel] [PATCH v2 53/60] target-i386: Remove gen_op_mov_TN_reg
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-devel] [PATCH v2 53/60] target-i386: Remove gen_op_mov_TN_reg |
|
Date: |
Fri, 29 Nov 2013 16:00:40 +1300 |
Replace with its definition, via Coccinelle.
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 111 +++++++++++++++++++++++-------------------------
1 file changed, 53 insertions(+), 58 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ab471b4..7f2c718 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -381,11 +381,6 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0,
int reg)
}
}
-static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg)
-{
- gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
-}
-
static inline void gen_op_movl_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
@@ -1088,7 +1083,7 @@ static int gen_jz_ecx_string(DisasContext *s,
target_ulong next_eip)
static inline void gen_stos(DisasContext *s, TCGMemOp ot)
{
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
@@ -1265,7 +1260,7 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
@@ -1331,7 +1326,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot,
int d)
static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
@@ -1401,7 +1396,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot,
int op1,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
@@ -1437,7 +1432,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot,
int op1, int op2,
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
op2 &= mask;
if (op2 != 0) {
@@ -1485,7 +1480,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot,
int op1, int is_right)
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
@@ -1571,7 +1566,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot,
int op1, int op2,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
op2 &= mask;
@@ -1649,7 +1644,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot,
int op1,
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
if (is_right) {
switch (ot) {
@@ -1705,7 +1700,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp
ot, int op1,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
count = tcg_temp_new();
@@ -1779,7 +1774,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp
ot, int op1,
static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
{
if (s != OR_TMP1)
- gen_op_mov_TN_reg(ot, 1, s);
+ gen_op_mov_v_reg(ot, cpu_T[1], s);
switch(op) {
case OP_ROL:
gen_rot_rm_T1(s1, ot, d, 0);
@@ -2057,10 +2052,10 @@ static void gen_ldst_modrm(CPUX86State *env,
DisasContext *s, int modrm,
if (mod == 3) {
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
if (reg != OR_TMP0)
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
@@ -2068,7 +2063,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext
*s, int modrm,
gen_lea_modrm(env, s, modrm);
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
@@ -4008,7 +4003,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
break;
case 0x20: /* pinsrb */
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
} else {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -4463,7 +4458,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
@@ -4477,7 +4472,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
}
gen_op(s, op, ot, reg);
break;
@@ -4557,7 +4552,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
@@ -4588,7 +4583,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
case 4: /* mul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4599,7 +4594,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4637,7 +4632,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
case 5: /* imul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4649,7 +4644,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4766,7 +4761,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
@@ -4856,7 +4851,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -4866,7 +4861,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
- gen_op_mov_TN_reg(ot, 0, OR_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], OR_EAX);
tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
@@ -4876,18 +4871,18 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
break;
#endif
case MO_32:
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_8, 0, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
@@ -4899,19 +4894,19 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_TN_reg(MO_64, 0, R_EAX);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
break;
#endif
case MO_32:
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
@@ -4938,7 +4933,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[1], val);
} else {
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
}
switch (ot) {
#ifdef TARGET_X86_64
@@ -4981,14 +4976,14 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -5082,7 +5077,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
- gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
+ gen_op_mov_v_reg(MO_32, cpu_T[0], (b & 7) | REX_B(s));
gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
@@ -5276,7 +5271,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
@@ -5342,7 +5337,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], R_EAX);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
}
}
@@ -5397,13 +5392,13 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
do_xchg_reg:
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
@@ -5523,7 +5518,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
if (shift) {
TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
@@ -6164,7 +6159,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
@@ -6198,7 +6193,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
@@ -6454,7 +6449,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
- gen_op_mov_TN_reg(MO_8, 0, R_AH);
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_AH);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
@@ -6502,7 +6497,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
/* load shift */
val = cpu_ldub_code(env, s->pc++);
@@ -6528,7 +6523,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(MO_32, 1, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[1], reg);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
/* specific case: we need to add a displacement */
@@ -6538,7 +6533,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
bt_op:
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
@@ -6786,7 +6781,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_lea_modrm(env, s, modrm);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -6800,13 +6795,13 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == MO_64) {
- gen_op_mov_TN_reg(MO_64, 0, reg);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
- gen_op_mov_TN_reg(MO_32, 0, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
@@ -7299,7 +7294,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
/* sign extend */
if (d_ot == MO_64)
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
@@ -7438,7 +7433,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
@@ -7475,7 +7470,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
goto illegal_op;
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
--
1.8.3.1
- [Qemu-devel] [PATCH v2 42/60] target-i386: Use gen_lea_v_seg in gen_lea_modrm, (continued)
- [Qemu-devel] [PATCH v2 42/60] target-i386: Use gen_lea_v_seg in gen_lea_modrm, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 43/60] target-i386: Use gen_lea_v_seg in stack subroutines, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 44/60] target-i386: Tidy cpu_regs initialization, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 45/60] target-i386: Access segs via TCG registers, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 33/60] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 48/60] target-i386: Introduce mo_stacksize, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 49/60] target-i386: Rewrite leave, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 50/60] target-i386: Remove gen_op_mov_reg_T0, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 51/60] target-i386: Remove gen_op_mov_reg_T1, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 52/60] target-i386: Remove gen_op_addl_T0_T1, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 53/60] target-i386: Remove gen_op_mov_TN_reg,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 54/60] target-i386: Remove gen_op_mov_reg_A0, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 55/60] target-i386: Remove gen_op_movl_A0_reg, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 57/60] target-i386: Tidy some size computation, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 58/60] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 59/60] target-i386: Tidy ljmp, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 60/60] target-i386: Deconstruct the cpu_T array, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 47/60] target-i386: Rewrite gen_enter inline, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 46/60] target-i386: Use gen_lea_v_seg in pusha/popa, Richard Henderson, 2013/11/28
- [Qemu-devel] [PATCH v2 34/60] target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp, Richard Henderson, 2013/11/28