From cd7c6f0130392c0c81064867e346b8a4b218e2cd Mon Sep 17 00:00:00 2001 From: Jan Petrous Date: Wed, 6 Nov 2013 12:38:58 +0100 Subject: [PATCH] arm: add pl030 rtc support Devboard Integrator/CP features RTC PL030. To get supported default kernel config for Integrator (integrator_defconfig) the PL030 RTC IP is added. Signed-off-by: Jan Petrous --- default-configs/arm-softmmu.mak | 1 + hw/arm/integratorcp.c | 2 +- hw/timer/Makefile.objs | 1 + hw/timer/pl030.c | 245 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 hw/timer/pl030.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 7e69137..87b9852 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -43,6 +43,7 @@ CONFIG_ARM_TIMER=y CONFIG_ARM_MPTIMER=y CONFIG_PL011=y CONFIG_PL022=y +CONFIG_PL030=y CONFIG_PL031=y CONFIG_PL041=y CONFIG_PL050=y diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index a759689..0f703b2 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -510,7 +510,7 @@ static void integratorcp_init(QEMUMachineInitArgs *args) sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); sysbus_create_varargs("integrator_pit", 0x13000000, pic[5], pic[6], pic[7], NULL); - sysbus_create_simple("pl031", 0x15000000, pic[8]); + sysbus_create_simple("pl030", 0x15000000, pic[8]); sysbus_create_simple("pl011", 0x16000000, pic[1]); sysbus_create_simple("pl011", 0x17000000, pic[2]); icp_control_init(0xcb000000); diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index eca5905..f4b4ea1 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -5,6 +5,7 @@ common-obj-$(CONFIG_DS1338) += ds1338.o common-obj-$(CONFIG_HPET) += hpet.o common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o common-obj-$(CONFIG_M48T59) += m48t59.o +common-obj-$(CONFIG_PL030) += pl030.o common-obj-$(CONFIG_PL031) += pl031.o common-obj-$(CONFIG_PUV3) += puv3_ost.o common-obj-$(CONFIG_TWL92230) += twl92230.o diff --git a/hw/timer/pl030.c b/hw/timer/pl030.c new file mode 100644 index 0000000..cee7a74 --- /dev/null +++ b/hw/timer/pl030.c @@ -0,0 +1,245 @@ +/* + * ARM AMBA PrimeCell PL030 RTC + * + * Tightly based on pl031.c QEMU sources (c) 2007 CodeSourcery + * Copyright (c) 2013 Tieto Corp., Jan Petrous + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" + +//#define DEBUG_PL030 + +#ifdef DEBUG_PL030 +#define DPRINTF(fmt, ...) \ +do { printf("pl030: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do {} while (0) +#endif + +#define RTC_DR 0x00 /* Data read register */ +#define RTC_MR 0x04 /* Match register */ +#define RTC_STAT 0x08 /* Masked interrupt status register */ +#define RTC_LR 0x0c /* Data load register */ +#define RTC_CR 0x10 /* Control register */ + +#define TYPE_PL030 "pl030" +#define PL030(obj) OBJECT_CHECK(PL030State, (obj), TYPE_PL030) + +typedef struct PL030State { + SysBusDevice parent_obj; + + MemoryRegion iomem; + QEMUTimer *timer; + qemu_irq irq; + + /* Needed to preserve the tick_count across migration, even if the + * absolute value of the rtc_clock is different on the source and + * destination. + */ + uint32_t tick_offset_vmstate; + uint32_t tick_offset; + + uint32_t mr; + uint32_t lr; + uint32_t cr; + uint32_t stat; +} PL030State; + +static const unsigned char pl030_id[] = { + 0x30, 0x10, 0x04, 0x00, /* Device ID */ + 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ +}; + +static void pl030_update(PL030State *s) +{ + qemu_set_irq(s->irq, s->stat); +} + +static void pl030_interrupt(void *opaque) +{ + PL030State *s = (PL030State *)opaque; + + s->stat = 1; + DPRINTF("Alarm raised\n"); + pl030_update(s); +} + +static uint32_t pl030_get_count(PL030State *s) +{ + int64_t now = qemu_clock_get_ns(rtc_clock); + return s->tick_offset + now / get_ticks_per_sec(); +} + +static void pl030_set_alarm(PL030State *s) +{ + uint32_t ticks; + + /* The timer wraps around. This subtraction also wraps in the same way, + and gives correct results when alarm < now_ticks. */ + ticks = s->mr - pl030_get_count(s); + DPRINTF("Alarm set in %ud ticks\n", ticks); + if (ticks == 0) { + timer_del(s->timer); + pl030_interrupt(s); + } else { + int64_t now = qemu_clock_get_ns(rtc_clock); + timer_mod(s->timer, now + (int64_t)ticks * get_ticks_per_sec()); + } +} + +static uint64_t pl030_read(void *opaque, hwaddr offset, + unsigned size) +{ + PL030State *s = (PL030State *)opaque; + + if (offset >= 0xfe0 && offset < 0x1000) + return pl030_id[(offset - 0xfe0) >> 2]; + + switch (offset) { + case RTC_DR: + return pl030_get_count(s); + case RTC_MR: + return s->mr; + case RTC_STAT: + return s->stat; + case RTC_LR: + return s->lr; + case RTC_CR: + /* RTC is permanently enabled. */ + return 1; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "pl030_read: Bad offset 0x%x\n", (int)offset); + break; + } + + return 0; +} + +static void pl030_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + PL030State *s = (PL030State *)opaque; + + + switch (offset) { + case RTC_LR: + s->tick_offset += value - pl030_get_count(s); + pl030_set_alarm(s); + break; + case RTC_MR: + s->mr = value; + pl030_set_alarm(s); + break; + case RTC_CR: + /* Written value is ignored. */ + break; + + case RTC_DR: + case RTC_STAT: + qemu_log_mask(LOG_GUEST_ERROR, + "pl030: write to read-only register at offset 0x%x\n", + (int)offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "pl030_write: Bad offset 0x%x\n", (int)offset); + break; + } +} + +static const MemoryRegionOps pl030_ops = { + .read = pl030_read, + .write = pl030_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static int pl030_init(SysBusDevice *dev) +{ + PL030State *s = PL030(dev); + struct tm tm; + + memory_region_init_io(&s->iomem, OBJECT(s), &pl030_ops, s, "pl030", 0x1000); + sysbus_init_mmio(dev, &s->iomem); + + sysbus_init_irq(dev, &s->irq); + qemu_get_timedate(&tm, 0); + s->tick_offset = mktimegm(&tm) - + qemu_clock_get_ns(rtc_clock) / get_ticks_per_sec(); + + s->timer = timer_new_ns(rtc_clock, pl030_interrupt, s); + return 0; +} + +static void pl030_pre_save(void *opaque) +{ + PL030State *s = opaque; + + /* tick_offset is base_time - rtc_clock base time. + * Instead we want to store the base time relative to the QEMU_CLOCK_VIRTUAL + * for backwards-compatibility. */ + int64_t delta = qemu_clock_get_ns(rtc_clock) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec(); +} + +static int pl030_post_load(void *opaque, int version_id) +{ + PL030State *s = opaque; + + int64_t delta = qemu_clock_get_ns(rtc_clock) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec(); + pl030_set_alarm(s); + return 0; +} + +static const VMStateDescription vmstate_pl030 = { + .name = "pl030", + .version_id = 1, + .minimum_version_id = 1, + .pre_save = pl030_pre_save, + .post_load = pl030_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT32(tick_offset_vmstate, PL030State), + VMSTATE_UINT32(mr, PL030State), + VMSTATE_UINT32(lr, PL030State), + VMSTATE_UINT32(cr, PL030State), + VMSTATE_UINT32(stat, PL030State), + VMSTATE_END_OF_LIST() + } +}; + +static void pl030_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = pl030_init; + dc->no_user = 1; + dc->vmsd = &vmstate_pl030; +} + +static const TypeInfo pl030_info = { + .name = TYPE_PL030, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PL030State), + .class_init = pl030_class_init, +}; + +static void pl030_register_types(void) +{ + type_register_static(&pl030_info); +} + +type_init(pl030_register_types) -- 1.7.11.3