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Re: [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation
From: |
Paolo Bonzini |
Subject: |
Re: [Qemu-devel] [PATCH 1/4] X86: Intel MPX definiation |
Date: |
Mon, 02 Dec 2013 18:39:07 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130923 Thunderbird/17.0.9 |
Il 02/12/2013 17:43, Liu, Jinsong ha scritto:
> From fbfa537f690eca139a96c6b2636ab5130bf57716 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong <address@hidden>
> Date: Fri, 29 Nov 2013 01:27:00 +0800
> Subject: [PATCH 1/4] X86: Intel MPX definiation
>
> Signed-off-by: Xudong Hao <address@hidden>
> Signed-off-by: Liu Jinsong <address@hidden>
> ---
> arch/x86/include/asm/cpufeature.h | 2 ++
> arch/x86/include/asm/xsave.h | 5 ++++-
> 2 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h
> b/arch/x86/include/asm/cpufeature.h
> index 89270b4..1b00b01 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -216,6 +216,7 @@
> #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
> #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
> #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional
> Memory */
> +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection
> Extension */
> #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
> #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX
> instructions */
> #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention
> */
> @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32];
> #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
> #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
> #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
> +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
> #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
> #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
>
> diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
> index 0415cda..d3e3ea5 100644
> --- a/arch/x86/include/asm/xsave.h
> +++ b/arch/x86/include/asm/xsave.h
> @@ -9,6 +9,8 @@
> #define XSTATE_FP 0x1
> #define XSTATE_SSE 0x2
> #define XSTATE_YMM 0x4
> +#define XSTATE_BNDREGS 0x8
> +#define XSTATE_BNDCSR 0x10
>
> #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
>
> @@ -23,7 +25,8 @@
> /*
> * These are the features that the OS can handle currently.
> */
> -#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
> +#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | \
> + XSTATE_BNDREGS | XSTATE_BNDCSR)
>
> #ifdef CONFIG_X86_64
> #define REX_PREFIX "0x48, "
>
The patches look good. Please include a cover letter (patch 0/n) next
time, and detail the changes from previous submissions.
It would also be nice to have support of the new feature for nested VMX
as well (including kvm-unit-tests coverage).
Paolo