[Qemu-devel] [PATCH 3/5] hw/intc: add allwinner A10 interrupt controller

[liguang]

Signed-off-by: liguang <address@hidden>
---
 hw/intc/Makefile.objs               |    1 +
 hw/intc/allwinner-a10_pic.c         |  218 +++++++++++++++++++++++++++++++++++
 include/hw/intc/allwinner-a10_pic.h |   40 +++++++
 3 files changed, 259 insertions(+), 0 deletions(-)
 create mode 100644 hw/intc/allwinner-a10_pic.c
 create mode 100644 include/hw/intc/allwinner-a10_pic.h

diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..65572d3 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -24,3 +24,4 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
 obj-$(CONFIG_SH4) += sh_intc.o
 obj-$(CONFIG_XICS) += xics.o
 obj-$(CONFIG_XICS_KVM) += xics_kvm.o
+obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10_pic.o
diff --git a/hw/intc/allwinner-a10_pic.c b/hw/intc/allwinner-a10_pic.c
new file mode 100644
index 0000000..e9322ee
--- /dev/null
+++ b/hw/intc/allwinner-a10_pic.c
@@ -0,0 +1,218 @@
+/*
+ * Allwinner A10 interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang <address@hidden>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/allwinner-a10_pic.h"
+
+
+static void a10_pic_update(A10PICState *s)
+{
+    uint8_t i, j;
+    bool irq = false, fiq = false;
+
+    for (i = 0, j = 0; i < A10_PIC_REG_NUM; i++) {
+        if (s->irq_pending[i] == 0 && s->fiq_pending[i] == 0) {
+            continue;
+        }
+        for (j = 0; j < 32; j++) {
+            if (test_bit(j, (void *)&s->mask[i])) {
+                continue;
+            }
+            if (test_bit(j, (void *)&s->irq_pending[i])) {
+                irq = true;
+            }
+            if (test_bit(j, (void *)&s->fiq_pending[i]) &&
+                test_bit(j, (void *)&s->select[i])) {
+                fiq = true;
+            }
+            if (irq && fiq) {
+                goto out;
+            }
+        }
+    }
+
+out:
+    qemu_set_irq(s->parent_irq, irq);
+    qemu_set_irq(s->parent_fiq, fiq);
+}
+
+static void a10_pic_set_irq(void *opaque, int irq, int level)
+{
+    A10PICState *s = opaque;
+
+    if (level) {
+        set_bit(irq%32, (void *)&s->irq_pending[irq/32]);
+    }
+    a10_pic_update(s);
+}
+
+static uint64_t a10_pic_read(void *opaque, hwaddr offset, unsigned size)
+{
+    A10PICState *s = opaque;
+    uint8_t index = (offset & 0xc)/4;
+
+    switch (offset) {
+    case A10_PIC_VECTOR:
+        return s->vector;
+    case A10_PIC_BASE_ADDR:
+        return s->base_addr;
+    case A10_PIC_PROTECT:
+        return s->protect;
+    case A10_PIC_NMI:
+        return s->nmi;
+    case A10_PIC_IRQ_PENDING ... A10_PIC_IRQ_PENDING + 8:
+        return s->irq_pending[index];
+    case A10_PIC_FIQ_PENDING ... A10_PIC_FIQ_PENDING + 8:
+        return s->fiq_pending[index];
+    case A10_PIC_SELECT ... A10_PIC_SELECT + 8:
+        return s->select[index];
+    case A10_PIC_ENABLE ... A10_PIC_ENABLE + 8:
+        return s->enable[index];
+    case A10_PIC_MASK ... A10_PIC_MASK + 8:
+        return s->mask[index];
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+        break;
+    }
+
+    return 0;
+}
+
+static void a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
+                             unsigned size)
+{
+    A10PICState *s = opaque;
+    uint8_t index = (offset & 0xc)/4;
+
+    switch (offset) {
+    case A10_PIC_VECTOR:
+        s->vector = value & ~0x3;
+        break;
+    case A10_PIC_BASE_ADDR:
+        s->base_addr = value & ~0x3;
+    case A10_PIC_PROTECT:
+        s->protect = value;
+        break;
+    case A10_PIC_NMI:
+        s->nmi = value;
+        break;
+    case A10_PIC_IRQ_PENDING ... A10_PIC_IRQ_PENDING + 8:
+        s->irq_pending[index] &= ~value;
+        break;
+    case A10_PIC_FIQ_PENDING ... A10_PIC_FIQ_PENDING + 8:
+        s->fiq_pending[index] &= ~value;
+        break;
+    case A10_PIC_SELECT ... A10_PIC_SELECT + 8:
+        s->select[index] = value;
+        break;
+    case A10_PIC_ENABLE ... A10_PIC_ENABLE + 8:
+        s->enable[index] = value;
+        break;
+    case A10_PIC_MASK ... A10_PIC_MASK + 8:
+        s->mask[index] = value;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+        break;
+    }
+
+    a10_pic_update(s);
+}
+
+static const MemoryRegionOps a10_pic_ops = {
+    .read = a10_pic_read,
+    .write = a10_pic_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_a10_pic = {
+    .name = "a10.pic",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(vector, A10PICState),
+        VMSTATE_UINT32(base_addr, A10PICState),
+        VMSTATE_UINT32(protect, A10PICState),
+        VMSTATE_UINT32(nmi, A10PICState),
+        VMSTATE_UINT32_ARRAY(irq_pending, A10PICState, A10_PIC_REG_NUM),
+        VMSTATE_UINT32_ARRAY(fiq_pending, A10PICState, A10_PIC_REG_NUM),
+        VMSTATE_UINT32_ARRAY(enable, A10PICState, A10_PIC_REG_NUM),
+        VMSTATE_UINT32_ARRAY(select, A10PICState, A10_PIC_REG_NUM),
+        VMSTATE_UINT32_ARRAY(mask, A10PICState, A10_PIC_REG_NUM),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void a10_pic_realize(DeviceState *ds, Error **errp)
+{
+    A10PICState *s = A10_PIC(ds);
+    SysBusDevice *dev = SYS_BUS_DEVICE(ds);
+
+     qdev_init_gpio_in(DEVICE(dev), a10_pic_set_irq, A10_PIC_INT_NR);
+     sysbus_init_irq(dev, &s->parent_irq);
+     sysbus_init_irq(dev, &s->parent_fiq);
+     memory_region_init_io(&s->iomem, OBJECT(s), &a10_pic_ops, s,
+                           "a10-pic", 0x400);
+     sysbus_init_mmio(dev, &s->iomem);
+}
+
+static void a10_pic_reset(DeviceState *d)
+{
+    A10PICState *s = A10_PIC(d);
+    uint8_t i;
+
+    s->base_addr = 0;
+    s->protect = 0;
+    s->nmi = 0;
+    s->vector = 0;
+    for (i = 0; i < A10_PIC_REG_NUM; i++) {
+        s->irq_pending[i] = 0;
+        s->fiq_pending[i] = 0;
+        s->select[i] = 0;
+        s->enable[i] = 0;
+        s->mask[i] = 0;
+    }
+}
+
+static void a10_pic_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = a10_pic_realize;
+    dc->reset = a10_pic_reset;
+    dc->desc = "A10 pic";
+    dc->vmsd = &vmstate_a10_pic;
+ }
+
+static const TypeInfo a10_pic_info = {
+    .name = TYPE_A10_PIC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(A10PICState),
+    .class_init = a10_pic_class_init,
+};
+
+static void a10_register_types(void)
+{
+    type_register_static(&a10_pic_info);
+}
+
+type_init(a10_register_types);
diff --git a/include/hw/intc/allwinner-a10_pic.h 
b/include/hw/intc/allwinner-a10_pic.h
new file mode 100644
index 0000000..9fd624b
--- /dev/null
+++ b/include/hw/intc/allwinner-a10_pic.h
@@ -0,0 +1,40 @@
+#ifndef A10_PIC_H
+#define A10_PIC_H
+
+#define TYPE_A10_PIC  "a10-pic"
+#define A10_PIC(obj) OBJECT_CHECK(A10PICState, (obj), TYPE_A10_PIC)
+
+#define A10_PIC_VECTOR         0
+#define A10_PIC_BASE_ADDR      4
+#define A10_PIC_PROTECT        8
+#define A10_PIC_NMI            0xc
+#define A10_PIC_IRQ_PENDING    0x10
+#define A10_PIC_FIQ_PENDING    0x20
+#define A10_PIC_SELECT 0x30
+#define A10_PIC_ENABLE 0x40
+#define A10_PIC_MASK           0x50
+
+#define A10_PIC_INT_NR 95
+#define A10_PIC_REG_NUM        DIV_ROUND_UP(A10_PIC_INT_NR, 32)
+
+typedef struct A10PICState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+    MemoryRegion iomem;
+    qemu_irq parent_fiq;
+    qemu_irq parent_irq;
+
+    uint32_t vector;
+    uint32_t base_addr;
+    uint32_t protect;
+    uint32_t nmi;
+    uint32_t irq_pending[A10_PIC_REG_NUM];
+    uint32_t fiq_pending[A10_PIC_REG_NUM];
+    uint32_t select[A10_PIC_REG_NUM];
+    uint32_t enable[A10_PIC_REG_NUM];
+    uint32_t mask[A10_PIC_REG_NUM];
+    /*priority setting here*/
+} A10PICState;
+
+#endif
-- 
1.7.2.5