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Re: [Qemu-devel] [PATCH 07/12] target-arm: A64: expand decoding skeleton
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH 07/12] target-arm: A64: expand decoding skeleton for system instructions |
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Date: |
Wed, 04 Dec 2013 12:49:48 +1300 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 |
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana <address@hidden>
>
> Decode the various kinds of system instructions:
> hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
> sync instructions, which include CLREX, DSB, DMB, ISB
> msr_i, which move immediate to processor state field
> sys, which include all SYS and SYSL instructions
> msr, which move from a gp register to a system register
> mrs, which move from a system register to a gp register
>
> Provide implementations where they are trivial nops.
>
> Signed-off-by: Claudio Fontana <address@hidden>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/translate-a64.c | 130
> +++++++++++++++++++++++++++++++++++++++++++-
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH 12/12] target-arm: A64: add support for compare and branch imm, (continued)
[Qemu-devel] [PATCH 08/12] target-arm: A64: add support for B and BL insns, Peter Maydell, 2013/12/03
[Qemu-devel] [PATCH 09/12] target-arm: A64: add support for BR, BLR and RET insns, Peter Maydell, 2013/12/03
[Qemu-devel] [PATCH 07/12] target-arm: A64: expand decoding skeleton for system instructions, Peter Maydell, 2013/12/03
[Qemu-devel] [PATCH 06/12] target-arm: A64: provide skeleton for a64 insn decoding, Peter Maydell, 2013/12/03