Re: [Qemu-devel] [PATCH 07/12] target-arm: A64: expand decoding skeleton for system instructions

[Peter Maydell]

On 3 December 2013 23:15, Christopher Covington <address@hidden> wrote:
> Hi Claudio, Peter,
>
> On 12/03/2013 04:51 PM, Peter Maydell wrote:
>> From: Claudio Fontana <address@hidden>
>>
>> Decode the various kinds of system instructions:
>>  hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
>>  sync instructions, which include CLREX, DSB, DMB, ISB
>>  msr_i, which move immediate to processor state field
>>  sys, which include all SYS and SYSL instructions
>>  msr, which move from a gp register to a system register
>>  mrs, which move from a system register to a gp register
>>
>> Provide implementations where they are trivial nops.
>>
>> Signed-off-by: Claudio Fontana <address@hidden>
>> Signed-off-by: Peter Maydell <address@hidden>
>> ---
>>  target-arm/translate-a64.c |  130 
>> +++++++++++++++++++++++++++++++++++++++++++-
> [...]
>> +/* C3.2.4 System */
>> +static void disas_system(DisasContext *s, uint32_t insn)
>> +{
>> +    /*
>> +     * 31 30 29 28 27 26 25 24 23 22 21 20 19 18   16 15   12 11   8 7   5 
>> 4  0
>> +     *  1  1  0  1  0  1  0  1  0  0  L  op0    op1     CRn     CRm   op2   
>> Rt
>> +     */
>
> [...]
>
> Could this opcode legend get a pretty box like the others?

Rats, I thought I caught them all in my review pass. Will fix.

-- PMM